IP Design Verification Director(Top30 Semconductor company in the world)

IP Design Verification Director
Top30 Semiconductor Organization in the world
Bangalore


Overvie

w
We are seeking a seasoned Director of Design Verification with 20+ years of experience to lead verification for a flagship product in our portfolio. This is a hands-on leadership role where you will define the verification strategy, oversee execution, and ensure first-pass silicon success for complex SoC designs in server, storage, and networking domain

s.
Key Responsibilit

ies
Own and drive the end-to-end verification methodology for a specific product l
ine.Lead, mentor, and grow a team of engineers, fostering technical excellence and innovat
ion.Guide verification of industry-standard protocols such as PCIe and CXL across Physical, Link, and Transaction lay
ers.Champion advanced methodologies (UVM, formal verification, AI-augmented flows) to accelerate coverage closure and improve efficie
ncy.Collaborate closely with RTL design, architecture, and software teams to debug, refine, and optimize verification proces
ses.Represent verification in executive reviews, customer engagements, and industry for
ums.Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges of the 20

30s.Qualificat

ions
Bachelor’s degree in Electrical or Computer Engineering (Master’s prefer
red).20+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon prod
ucts.Deep expertise in PCIe/CXL protocols (Gen3 and above) and experience with third-party Verification
IPs.Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer de
sign.Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational suc

cess.Required Exper

ience
Hands-on expertise with Verification IPs for PCIe/CXL (Gen3 and a
bove).Deep experience in UVM-based test plan development, sequence generation, and coverage ana
lysis.Strong background in writing assertions, cover properties, and analyzing coverage
data.Experience in developing VIP abstraction layers to simplify and scale verification deploy

ments.Preferred Expe

rience
Expertise in verifying PCIe / CXL Physical, Link, and Transaction layers, including compliance for
EP/RC.Experience with buffering, queuing, and QoS in complex NoC-base
d SoCs.System-level performance analysis on switching f
abrics.Familiarity with AI-driven verification methodologies and workforce transformation stra

tegies.
Cont
act:Ud
ayMulya Tech
nologiesmuday_bhaskar@y
ahoo.com
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