N
Internship / Master Thesis Opportunity – Analog & RFIC Design for Sub-THz Communication Systems
Accepting applicationsNXP · Eindhoven, Netherlands, Europe
Full-Time Entry AnalogCMOSCadenceRFanalog
Posted
9 Jul
Category
Design
Experience
Entry
Country
Netherlands
The Future Starts Here. Ready to Join NXP?
Join NXP's Innovation Team in Eindhoven and help shape the next generation of wireless communication systems. As an intern or master thesis student, you will contribute to the design and evaluation of state-of-the-art mm-wave and sub-THz integrated circuits for future high-speed wireless interconnect and sensing applications.
Your Role
- Design and analyze analog/RF building blocks operating at mm-wave and sub-THz frequencies.
- Perform circuit simulation, modeling, optimization, and performance evaluation.
- Collaborate with experts in RFIC, antenna, packaging, and communication system design.
- Contribute to innovative solutions addressing real industrial challenges and future product opportunities.
What's in It for You
- Opportunity to conduct your internship as an MSc thesis project.
- Work alongside one of the world's leading mm-wave and sub-THz IC design teams.
- Gain hands-on experience with advanced CMOS technologies and industrial RFIC design flows.
- Contribute to cutting-edge research with direct impact on future semiconductor products.
- Opportunity to publish, innovate, and contribute to invention disclosures.
Your Profile
- MSc student in Microelectronics
- Strong interest in analog, RF, and mm-wave integrated circuit design.
- Experience with Cadence, circuit simulation, electromagnetics, or communication systems is a plus.
- Curious, self-driven, and eager to tackle challenging engineering problems.
Duration: 9–12 months (Internship and MSc Thesis possible)
Similar Jobs
I
RTL Design Engineer
Intel · Hillsboro, United States, North America
N
NVIDIA 2027 New College Graduate: Hardware ASIC Engineering - China
NVIDIA · Shanghai, China, Asia
N
ASIC Methodology, Flow and Integration Engineer
NVIDIA · 2 Locations
N
Physical Design Power Optimization and Modeling Engineer
NVIDIA · 2 Locations