MC
Immediate Job Opening for RTL Design ( SOC integration) for BLR Location
Accepting applicationsModernize Chip Solutions (MCS) · Bengaluru, Karnataka, India
Full-Time Mid_senior SystemVerilogRTLCDCAPBSOC Integration
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
India
Hi All,
We are urgent hiring RTL Design ( SOC Integration) for BLR location.
Exp - 7+ yrs
Notice Period - Immediate to 30 days
Job Location - BLR
Jd:
Authoring and owning 3rd party IP integration.
• Multi-domain CDC analysis
• ASEP 8-port interface: 32-to-16-bit width adaptation, async FIFO design, stype routing, SOP/EOP framing
• APB/SOC slave bus bridge; register map ownership; RGGEN-based CSR methodology
• System Verilog (RTL and assertions), lint (Cadence HAL/SpyGlass), linting closure, cadence CDC tool
• Working knowledge of ASA-ML DLL, PCS, OAM, PTB, and ASEP layers; PHY datasheet/spec fluency
• Add MBIST/LBIST and redundancy etc. safety mechanism to make whole chip complied to FuSa requirements
Interested candidates, kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com or ping me 9900927620 for detailed discussion.
Show more Show less
We are urgent hiring RTL Design ( SOC Integration) for BLR location.
Exp - 7+ yrs
Notice Period - Immediate to 30 days
Job Location - BLR
Jd:
Authoring and owning 3rd party IP integration.
• Multi-domain CDC analysis
• ASEP 8-port interface: 32-to-16-bit width adaptation, async FIFO design, stype routing, SOP/EOP framing
• APB/SOC slave bus bridge; register map ownership; RGGEN-based CSR methodology
• System Verilog (RTL and assertions), lint (Cadence HAL/SpyGlass), linting closure, cadence CDC tool
• Working knowledge of ASA-ML DLL, PCS, OAM, PTB, and ASEP layers; PHY datasheet/spec fluency
• Add MBIST/LBIST and redundancy etc. safety mechanism to make whole chip complied to FuSa requirements
Interested candidates, kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com or ping me 9900927620 for detailed discussion.
Show more Show less