Immediate hiring for Asic DV engineers for BLR Location

Hi All,

I have urgent opening for Design Verification ( IP) for one of our Client in BLR location.

Exp 5+ yrs
Location - BLR
Client - Product Client.
NP - Immediate to 15 days (MAX)
JD:
Key Skills:
Strong System Verilog (SV) and UVM expertise
Verification of PCIe Gen4/Gen5/Gen6 and/or CXL protocols(Mandatory)
Testbench development, Scoreboards, Assertions, Functional Coverage
Protocol debugging and regression analysis
Experience with VCS/Xcelium/Questa and Verdi

Interested candidates, Kindly share with me your updated profile to anand.arumugam@modernchipsolutions.com or Ping me 9900927620 for detailed discussion
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