MC
Imemdiate Job opening for DFT Engineers for BLR location
Accepting applicationsModernize Chip Solutions (MCS) · Bengaluru, Karnataka, India
Full-Time Mid_senior DFTScanTessentPHY DFTBoundary Scan
Posted
3d ago
Category
Test
Experience
Mid_senior
Country
India
Hi All,
We are currently hiring senior DFT Engineers for BLR Location.
Exp - 7+ yrs
Location - BLR
Notice Period - Immediate to 30 days
JD:
Design-for-test architecture, insertion, and signoff for the full chip including PHY and third-party IP DFT boundary conditions.
• Scan chain insertion and compression (Tessent) across multi-clock digital logic
• ASA PHY DFT integration
• ASA IP DFT ports
• BIST PCS-PMA bus isolation
• Memory BIST (MBIST) for internal SRAMs/FIFOs; ATPG pattern generation and fault simulation.
• IEEE 1149.1 JTAG controller integration; boundary scan for automotive test coverage
• Siemens Tessent or Synopsys DFT Compiler; prior automotive-grade DFT (AEC-Q100) experience preferred
Interested candidates, Kindly reach me 9900927620 or share with me your updated profile to anand.arumugam@modernchipsolutions.com
Show more Show less
We are currently hiring senior DFT Engineers for BLR Location.
Exp - 7+ yrs
Location - BLR
Notice Period - Immediate to 30 days
JD:
Design-for-test architecture, insertion, and signoff for the full chip including PHY and third-party IP DFT boundary conditions.
• Scan chain insertion and compression (Tessent) across multi-clock digital logic
• ASA PHY DFT integration
• ASA IP DFT ports
• BIST PCS-PMA bus isolation
• Memory BIST (MBIST) for internal SRAMs/FIFOs; ATPG pattern generation and fault simulation.
• IEEE 1149.1 JTAG controller integration; boundary scan for automotive test coverage
• Siemens Tessent or Synopsys DFT Compiler; prior automotive-grade DFT (AEC-Q100) experience preferred
Interested candidates, Kindly reach me 9900927620 or share with me your updated profile to anand.arumugam@modernchipsolutions.com
Show more Show less