IC Packaging Design Engineer

We are seeking a highly skilled and detail-oriented Silicon Substrate Design Engineer to drive the physical design and layout implementation of next-generation 2D, 2.5D and 3D heterogeneous packaging architectures. Specializing in Silicon Interposer and Redistribution Layer (RDL) technologies, you will collaborate closely with ASIC architecture, foundry partners, OSATs, and Signal/Power Integrity (SI/PI) teams to deliver robust, high-density interconnect solutions for high-performance computing (HPC), AI accelerators, and high-speed networking applications.

Skills : IC Package Design & 2D, 2.5D & 3D packaging architectures is a must

Key Responsibilities
● Physical Layout & Routing: Own the end-to-end physical design, floor planning, and layout of passive/active silicon interposers and high-density RDL fan-out packages.1
● High-Density Interconnects: Execute complex routing for ultra-fine-pitch microbumps, C4 bumps, TSVs (Through-Silicon Vias), microvias, and pillar structures.1
● Interface Implementation: Route critical high-speed, high-bandwidth interfaces such as HBM, PCIe Gen 5/Gen 6, and die-to-die interfaces with stringent impedance controls.1
● Design Optimization: Actively drive die-package-board co-optimization (DPCO) by mapping bump assignments and floorplans across multiple disparate chiplets.1
● Constraint Implementation: Incorporate layout constraints provided by SI/PI teams, optimizing power delivery networks (PDN) and implementing shielding strategies to minimize crosstalk, insertion loss, and IR drop.1
● Verification: Run and resolve comprehensive physical verification checks, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), connectivity, and antenna rules.1
● DFM & Yield: Collaborate with leading silicon foundries and OSATs to ensure strict alignment
with Design for Manufacturing (DFM), Design for Assembly (DFA), and reliability standards to maximize production yields.1

Required Skills & Qualifications Technical Expertise
● Deep understanding of 2.5D/3D advanced packaging architectures, wafer-level packaging (WLP), and substrate technologies.1
● Mastery of layout routing constraints, stack-up optimization, and silicon processing limits (e.g., fine-line/space lithography down to sub-micron scales for RDL).1
● Solid grasp of electromagnetic and transmission line fundamentals, signal integrity constraints, and thermal-mechanical stress factors in silicon-interposer assemblies.1 Tool & EDA Proficiency
● Extensive hands-on experience with advanced IC packaging and IC layout tools, including:
● Cadence Suite: APD, Allegro Package Designer Plus, Innovus, Virtuoso.1
● Verification: Siemens EDA Calibre, Ansys (HFSS/SIwave for layout review), and IC Validator.1

Soft Skills & Experience
● Excellent cross-functional communication skills, with a proven ability to bridge gaps between silicon design teams and manufacturing foundries.1
● Strong debugging and problem-solving skills when addressing complex DRC violations and multi-die routing bottlenecks.1

Education & Experience Requirements
● Education: Bachelor’s, Master’s, or Ph.D. in Electrical Engineering, Electronics, Microelectronics, Materials Science, or a closely related field.1
● Experience (Engineer): 3+ years of experience in silicon physical design or IC package layout.1
● Experience (Senior/Staff Engineer): 6–10+ years of hands-on experience delivering production-ready 2.5D/3D interposer or high-density fan-out (HDFO) designs from concept to tape-ou
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