I
IBM LOGIC DESIGN ENGINEER – Processor Coherency Logic
Accepting applicationsIBM · Bengaluru, Karnataka, India
Full-Time Mid_senior RTL
Posted
12 Jun
Category
Design
Experience
Mid_senior
Country
India
Introduction
At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.
Your Role And Responsibilities
Lead the design and development of on- and off-chip network microarchitectures for Coherency and data transport that meet KPIs for next-generation SMP.
Work closely with Cache/Nest PD architect & designers to implement structures/topologies that are logically and physically realizable by the target tape-out date.
Modify/develop Cache Coherence protocol that best supports coherence transport topology.
Develop features in L2 and LLC micro architectures that improve KPIs.
Work with Core Architects & Designers to implement features in L2-Core interface and interactions, that improves KPIs.
Preferred Education
Master's Degree
Required Technical And Professional Expertise
Minimum 8 to 12 years of relevant experience
Hands-on RTL level experience of independently delivering Coherency feature in processor
Expertise in Cache Coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP
Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations
Experience in working with Core architecture/ FW/ SW teams
Exposure to System microarchitecture
Preferred Technical And Professional Experience
Knowledge of Memory Management units, Data transfer protocols
Knowledge of CDC, RDC concepts
Knowledge of verification principles and coverage
High-level knowledge of Linux operating system
Knowledge of one object oriented language and scripting language
Understanding of Agile development processes
Experience with DevOps design methodologies and tools
Show more Show less
At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.
Your Role And Responsibilities
Lead the design and development of on- and off-chip network microarchitectures for Coherency and data transport that meet KPIs for next-generation SMP.
Work closely with Cache/Nest PD architect & designers to implement structures/topologies that are logically and physically realizable by the target tape-out date.
Modify/develop Cache Coherence protocol that best supports coherence transport topology.
Develop features in L2 and LLC micro architectures that improve KPIs.
Work with Core Architects & Designers to implement features in L2-Core interface and interactions, that improves KPIs.
Preferred Education
Master's Degree
Required Technical And Professional Expertise
Minimum 8 to 12 years of relevant experience
Hands-on RTL level experience of independently delivering Coherency feature in processor
Expertise in Cache Coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP
Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations
Experience in working with Core architecture/ FW/ SW teams
Exposure to System microarchitecture
Preferred Technical And Professional Experience
Knowledge of Memory Management units, Data transfer protocols
Knowledge of CDC, RDC concepts
Knowledge of verification principles and coverage
High-level knowledge of Linux operating system
Knowledge of one object oriented language and scripting language
Understanding of Agile development processes
Experience with DevOps design methodologies and tools
Show more Show less
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