IBM LOGIC DESIGN ENGINEER – Core Instruction Sequencing Unit

Introduction

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You’ll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.

Your Role And Responsibilities

Lead the design and development of Instruction Sequencing Unit for high-performance Processor CPU of IBM Systems.
Architect and design Instruction Dispatch to Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of a high performance processor CPU
Develop the features, present the proposed architecture in the High level design discussions
Estimate the overall effort to develop the feature.
Estimate silicon area and wire usage for the feature.
Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature
Signoff the Pre-silicon Design that meets all the functional, area and timing goals
Participate in post silicon lab bring-up and validation of the hardware
Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums.

Preferred Education

Master's Degree

Required Technical And Professional Expertise

8 to 12 or more years of demonstrated experience in architecting and designing Out-of-Order unit of CPU
Hands of experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling
Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA
Experience with high frequency, instruction pipeline designs
At least 1 generation of Processor Core silicon bring up experience
In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs)
Proficiency of RTL design with Verilog or VHDL

Preferred Technical And Professional Experience

Knowledge of Instruction Fetch & Decode and Execution units
Knowledge of verification principles and coverage
High-level knowledge of Linux operating system
Knowledge of one object oriented language and scripting language
Understanding of Agile development processes
Experience with DevOps design methodologies and tools
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