B
I.C Design Engineer
Accepting applicationsBroadcom · San Jose, CA
Full-Time Entry ASICRTLaiaterf
Posted
2d ago
Category
Design
Experience
Entry
Country
United States
Job Description
As a member of the ASIC Implementation team, you will be part of the team implementing new technologies in a variety of exciting consumer electronic devices. You will be directly involved in:
Leading a Synthesis and Timing of complex designs, provide guidance, interface with
RTL team for quality RTL delivery
Full chip and Block constraints development and constraints generation.
Full chip and Block Synthesis, STA and timing closure
Interfacing with internal external teams including Design, IP, Library
Methodology & Flow development of Synthesis, Formality, STA, Low power checks &
Timing Closure:
Working independently with the PNR & RTL design team on Physical
implementation and Power-intent requirements
Requirement:
Should have done multiple Tapeouts, have extensive experience in frontend tools such
as Primerime, DC, VCLP, Formality, LEC, Timing closure and timing
Extensive knowledge of PT/DC is important. Good in tcl scripting.
Bachelors in Engineering and 12+ years of related experience or Masters degree in Engineering and 10+ years of related experience
Show more Show less
As a member of the ASIC Implementation team, you will be part of the team implementing new technologies in a variety of exciting consumer electronic devices. You will be directly involved in:
Leading a Synthesis and Timing of complex designs, provide guidance, interface with
RTL team for quality RTL delivery
Full chip and Block constraints development and constraints generation.
Full chip and Block Synthesis, STA and timing closure
Interfacing with internal external teams including Design, IP, Library
Methodology & Flow development of Synthesis, Formality, STA, Low power checks &
Timing Closure:
Working independently with the PNR & RTL design team on Physical
implementation and Power-intent requirements
Requirement:
Should have done multiple Tapeouts, have extensive experience in frontend tools such
as Primerime, DC, VCLP, Formality, LEC, Timing closure and timing
Extensive knowledge of PT/DC is important. Good in tcl scripting.
Bachelors in Engineering and 12+ years of related experience or Masters degree in Engineering and 10+ years of related experience
Show more Show less