JV
Hiring Physical Design Engineer in California
Accepting applicationsJobs via Dice · Santa Clara, CA
Full-Time Mid CadenceDFTPerlRTLSoC
Posted
1d ago
Category
Design
Experience
Mid
Country
United States
Dice is the leading career destination for tech experts at every stage of their careers. Our client, CaritaTech LLC., is seeking the following. Apply via Dice today!
Hi,
Job Title: Physical Design Engineer
Location: Cupertino, CA
Work Mode: 100% Onsite (5 Days/Week)
Experience: 5 15Years
Job Description
We are actively hiring experienced Physical Design Engineers for a leading semiconductor client in Cupertino, CA. Candidates should possess strong expertise in end-to-end physical implementation and signoff flows for advanced node SoC designs.
Responsibilities
Execute complete physical design implementation flow including Floorplanning, Power Planning, Placement, CTS, Routing, and Timing Closure.
Perform Signal Integrity, Power Integrity, EM/IR, DRC/LVS, Antenna, and DFM signoff activities.
Handle block-level and full-chip implementation for advanced SoC designs.
Drive timing convergence and physical signoff closure.
Collaborate with RTL, STA, DFT, and Verification teams throughout implementation cycles.
Optimize PPA (Power, Performance, Area) across implementation stages.
Develop automation flows and methodology improvements using scripting.
Required Skills
Strong experience with Cadence and Synopsys physical design tool suites.
Expertise in STA and timing signoff using Synopsys PrimeTime.
Hands-on experience with advanced nodes such as 7nm/5nm/3nm.
Strong knowledge of Place & Route, CTS, Timing Closure, and Physical Verification.
Scripting expertise in TCL, Perl, Shell, and Make.
Excellent debugging and analytical skills.
Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, or VLSI.
Apply Now
Looking for immediate joiners or candidates available within short notice.
Show more Show less
Hi,
Job Title: Physical Design Engineer
Location: Cupertino, CA
Work Mode: 100% Onsite (5 Days/Week)
Experience: 5 15Years
Job Description
We are actively hiring experienced Physical Design Engineers for a leading semiconductor client in Cupertino, CA. Candidates should possess strong expertise in end-to-end physical implementation and signoff flows for advanced node SoC designs.
Responsibilities
Execute complete physical design implementation flow including Floorplanning, Power Planning, Placement, CTS, Routing, and Timing Closure.
Perform Signal Integrity, Power Integrity, EM/IR, DRC/LVS, Antenna, and DFM signoff activities.
Handle block-level and full-chip implementation for advanced SoC designs.
Drive timing convergence and physical signoff closure.
Collaborate with RTL, STA, DFT, and Verification teams throughout implementation cycles.
Optimize PPA (Power, Performance, Area) across implementation stages.
Develop automation flows and methodology improvements using scripting.
Required Skills
Strong experience with Cadence and Synopsys physical design tool suites.
Expertise in STA and timing signoff using Synopsys PrimeTime.
Hands-on experience with advanced nodes such as 7nm/5nm/3nm.
Strong knowledge of Place & Route, CTS, Timing Closure, and Physical Verification.
Scripting expertise in TCL, Perl, Shell, and Make.
Excellent debugging and analytical skills.
Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, or VLSI.
Apply Now
Looking for immediate joiners or candidates available within short notice.
Show more Show less