TM
Hiring For Design Verification Engineer
Accepting applicationsTech Mahindra · Greater Bengaluru Area
Full-Time Mid_senior PCIePerlPower ManagementPythonRTL
Posted
21h ago
Category
Design
Experience
Mid_senior
Country
India
Hi Everyone
We are hiring For Design Verification and GLS Engineer
Exp: 4 to 12 Years
Np: Immediate to 30 days
Key skills: UVM, SV, Verilog, High speed protocols and Power Management (Plus advantage)
Key Responsibilities
Develop directed and constrained-random testcases
Debug failures and root-cause issues across RTL, testbench, and tools
RTL as well as Gate level simulations
Automate regression flows and improve verification productivity
Required Skills & Qualifications
Technical Skills
Good knowledge of SystemVerilog
Hands-on experience with UVM (Universal Verification Methodology)
Experience with EDA tools (e.g., VCS, Verdi)
Experience in debugging RTL and gate level simulation issues
Good knowledge of PCIe protocol
Programming/Scripting
Proficiency in Python/Perl/Shell scripting for automation
Show more Show less
We are hiring For Design Verification and GLS Engineer
Exp: 4 to 12 Years
Np: Immediate to 30 days
Key skills: UVM, SV, Verilog, High speed protocols and Power Management (Plus advantage)
Key Responsibilities
Develop directed and constrained-random testcases
Debug failures and root-cause issues across RTL, testbench, and tools
RTL as well as Gate level simulations
Automate regression flows and improve verification productivity
Required Skills & Qualifications
Technical Skills
Good knowledge of SystemVerilog
Hands-on experience with UVM (Universal Verification Methodology)
Experience with EDA tools (e.g., VCS, Verdi)
Experience in debugging RTL and gate level simulation issues
Good knowledge of PCIe protocol
Programming/Scripting
Proficiency in Python/Perl/Shell scripting for automation
Show more Show less