ED
Hiring DFT Leads/Managers for Bangalore Location
Accepting applicationsEximietas Design · Bengaluru, Karnataka, India
Full-Time Mid_senior ATPGBISTBoundary ScanDFTJTAG
Posted
5d ago
Category
Test
Experience
Mid_senior
Country
India
Senior DFT Engineer / Lead DFT Engineer/Manager DFT Engineer – SSN & SoC DFT
Location: Bangalore / Hyderabad / Ahmedabad
Experience: 6+ Years
Position Overview
We are seeking an experienced DFT Engineer with strong expertise in full-chip SoC DFT implementation, Scan Insertion, MBIST, ATPG, and Siemens Tessent SSN (Streaming Scan Network) methodologies. The ideal candidate will drive end-to-end DFT execution for complex, high-performance SoCs while optimizing test cost, test time, and silicon quality.
Key Responsibilities
Lead full-chip and SoC-level Scan Insertion, ATPG, and test compression implementation using Siemens Tessent/TestKompress.
Architect and deploy Streaming Scan Network (SSN) solutions, including packet delivery configuration, bus-width allocation, and test infrastructure optimization.
Implement and verify MBIST, memory grouping, custom BIST controllers, and BISR solutions.
Generate and optimize ATPG patterns for Stuck-at, Transition, and Cell-Aware fault models.
Execute low-power ATPG methodologies to reduce switching activity and IR-drop related issues.
Perform DFT verification using GLS (Zero Delay & SDF Timing Simulations).
Define and validate DFT timing constraints for Shift, Capture, and MBIST modes.
Collaborate with Design, Physical Design, Synthesis, and STA teams to ensure successful DFT integration and sign-off.
Develop and enhance DFT automation flows using Tcl, Python, or Perl.
Required Skills
✅ 6+ years of hands-on DFT experience in advanced SoCs
✅ Strong expertise in Scan, ATPG, MBIST, and DFT Verification
✅ Extensive experience with Siemens Tessent Suite:
Tessent Shell
TestKompress
Tessent MemoryBIST
Tessent SSN
✅ Deep understanding of SSN architecture and packetized test delivery methodologies
✅ Experience with IEEE 1500, Boundary Scan (JTAG), and hierarchical DFT architectures
✅ Proficiency in VCS, Questa, or Xcelium for simulation and debug
✅ Strong scripting skills in Tcl and Python/Perl
✅ Experience working closely with Physical Design and STA teams for DFT timing closure
Education
Bachelor's or Master's degree in Electrical, Electronics, Computer Engineering, or related field.
Why Join Us?
Work on cutting-edge, high-performance SoC designs.
Drive next-generation DFT methodologies including SSN and advanced test architectures.
Collaborate with industry-leading design and implementation teams.
Opportunity to influence silicon quality and production readiness for complex semiconductor products.
📩 Interested candidates can share their updated resume to balachowdaiah.p@eximietas.design.
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Location: Bangalore / Hyderabad / Ahmedabad
Experience: 6+ Years
Position Overview
We are seeking an experienced DFT Engineer with strong expertise in full-chip SoC DFT implementation, Scan Insertion, MBIST, ATPG, and Siemens Tessent SSN (Streaming Scan Network) methodologies. The ideal candidate will drive end-to-end DFT execution for complex, high-performance SoCs while optimizing test cost, test time, and silicon quality.
Key Responsibilities
Lead full-chip and SoC-level Scan Insertion, ATPG, and test compression implementation using Siemens Tessent/TestKompress.
Architect and deploy Streaming Scan Network (SSN) solutions, including packet delivery configuration, bus-width allocation, and test infrastructure optimization.
Implement and verify MBIST, memory grouping, custom BIST controllers, and BISR solutions.
Generate and optimize ATPG patterns for Stuck-at, Transition, and Cell-Aware fault models.
Execute low-power ATPG methodologies to reduce switching activity and IR-drop related issues.
Perform DFT verification using GLS (Zero Delay & SDF Timing Simulations).
Define and validate DFT timing constraints for Shift, Capture, and MBIST modes.
Collaborate with Design, Physical Design, Synthesis, and STA teams to ensure successful DFT integration and sign-off.
Develop and enhance DFT automation flows using Tcl, Python, or Perl.
Required Skills
✅ 6+ years of hands-on DFT experience in advanced SoCs
✅ Strong expertise in Scan, ATPG, MBIST, and DFT Verification
✅ Extensive experience with Siemens Tessent Suite:
Tessent Shell
TestKompress
Tessent MemoryBIST
Tessent SSN
✅ Deep understanding of SSN architecture and packetized test delivery methodologies
✅ Experience with IEEE 1500, Boundary Scan (JTAG), and hierarchical DFT architectures
✅ Proficiency in VCS, Questa, or Xcelium for simulation and debug
✅ Strong scripting skills in Tcl and Python/Perl
✅ Experience working closely with Physical Design and STA teams for DFT timing closure
Education
Bachelor's or Master's degree in Electrical, Electronics, Computer Engineering, or related field.
Why Join Us?
Work on cutting-edge, high-performance SoC designs.
Drive next-generation DFT methodologies including SSN and advanced test architectures.
Collaborate with industry-leading design and implementation teams.
Opportunity to influence silicon quality and production readiness for complex semiconductor products.
📩 Interested candidates can share their updated resume to balachowdaiah.p@eximietas.design.
Show more Show less