JV
Hiring DFT Engineer in California
Accepting applicationsJobs via Dice · Santa Clara, CA
Full-Time Mid ASICATPGBISTBoundary ScanDFT
Posted
1d ago
Category
Test
Experience
Mid
Country
United States
Dice is the leading career destination for tech experts at every stage of their careers. Our client, CaritaTech LLC., is seeking the following. Apply via Dice today!
Hi,
Job Title: DFT Engineer (Design for Test)
Location: Santa Clara, CA
Work Mode: Hybrid / Onsite
Job Description
We are seeking skilled DFT Engineers with strong expertise in SoC/ASIC test methodologies and ATPG flows for advanced semiconductor programs.
Responsibilities
Design and implement DFT architecture for complex SoC and ASIC designs.
Integrate and validate Scan, MBIST, LBIST, JTAG, Boundary Scan, and ATPG methodologies.
Generate and debug ATPG patterns for stuck-at and transition fault coverage.
Collaborate with RTL, PD, and Verification teams for testability closure.
Perform DFT verification using simulation and formal validation techniques.
Support silicon bring-up, diagnosis, and yield improvement activities.
Optimize test coverage while balancing timing, power, and area constraints.
Required Skills
Hands-on experience with Synopsys Tessent, DFT Compiler, TetraMAX, or equivalent DFT tools.
Strong understanding of scan insertion, compression, MBIST, LBIST, and ATPG flows.
Experience with hierarchical and SoC-level DFT methodologies.
Knowledge of Verilog/SystemVerilog and scripting using TCL, Perl, or Python.
Familiarity with low-power DFT techniques and advanced technology nodes.
Strong debugging and problem-solving skills.
Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, or VLSI.
Apply Now
Excellent opportunity to work on cutting-edge semiconductor technologies with a high-growth engineering team.
Show more Show less
Hi,
Job Title: DFT Engineer (Design for Test)
Location: Santa Clara, CA
Work Mode: Hybrid / Onsite
Job Description
We are seeking skilled DFT Engineers with strong expertise in SoC/ASIC test methodologies and ATPG flows for advanced semiconductor programs.
Responsibilities
Design and implement DFT architecture for complex SoC and ASIC designs.
Integrate and validate Scan, MBIST, LBIST, JTAG, Boundary Scan, and ATPG methodologies.
Generate and debug ATPG patterns for stuck-at and transition fault coverage.
Collaborate with RTL, PD, and Verification teams for testability closure.
Perform DFT verification using simulation and formal validation techniques.
Support silicon bring-up, diagnosis, and yield improvement activities.
Optimize test coverage while balancing timing, power, and area constraints.
Required Skills
Hands-on experience with Synopsys Tessent, DFT Compiler, TetraMAX, or equivalent DFT tools.
Strong understanding of scan insertion, compression, MBIST, LBIST, and ATPG flows.
Experience with hierarchical and SoC-level DFT methodologies.
Knowledge of Verilog/SystemVerilog and scripting using TCL, Perl, or Python.
Familiarity with low-power DFT techniques and advanced technology nodes.
Strong debugging and problem-solving skills.
Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, or VLSI.
Apply Now
Excellent opportunity to work on cutting-edge semiconductor technologies with a high-growth engineering team.
Show more Show less