A
High-Level Synthesis (HLS) Engineer
Accepting applicationsAltera · San Jose, CA
Full-Time Mid_senior AIASICC++FPGARTL
Posted
3d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Details
Job Description:
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About The Role
Altera is at the forefront of programmable logic and hardware acceleration. Our mission is to empower developers and system architects to rapidly design and deploy next-generation systems using advanced FPGA and SoC technologies.
Within Altera, the High-Level Synthesis (HLS) team builds cutting-edge compiler systems that bridge the gap between software and hardware. We transform high-level programming models into highly optimized hardware implementations, enabling breakthroughs in AI, cloud infrastructure, and domain-specific acceleration.
We are looking for talent who are excited to push the boundaries of compilers, systems, and hardware/software co-design.
What You’ll Work On
As a member of the HLS research and engineering team, you will contribute to both production compiler systems and forward-looking research:
Design and develop next-generation compiler infrastructure for HLS
Invent and implement novel compiler passes, optimizations, and code transformations for hardware synthesis
Explore advanced compilation techniques for AI/ML workloads, including graph-level and system-level optimizations
Improve end-to-end compilation flow from C/C++ (and beyond) to RTL, focusing on performance, power, and area efficiency
Prototype and evaluate new ideas in collaboration with research and product teams
Contribute to publications, patents, and internal technical innovations
Work closely with hardware architects and domain experts to co-design future acceleration platforms
What We Offer
A collaborative environment where research ideas turn into shipped products
Competitive compensation and benefits
Opportunities for career growth in both research and engineering tracks
A culture that values innovation, ownership, and technical excellence
Salary
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$133.2K - $192.8K USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
#CG-1
Qualifications
Minimum Qualifications
Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field, with 3+ years of experience
Strong foundation in one or more of the following:
Compiler design (e.g., optimization, IR design, code generation)
Programming languages or systems
Computer architecture or digital design
Proficiency in C/C++ or similar systems programming languages
Preferred Qualifications
Research experience in compilers, HLS, or hardware/software co-design
Familiarity with LLVM, MLIR, or similar compiler infrastructures
Exposure to FPGA/ASIC design flows or hardware description languages (Verilog/VHDL)
Background in optimizing AI/ML workloads or domain-specific accelerators
Publications in relevant conferences or demonstrated research impact
Job Type
Regular
Shift
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Job Description:
About Altera
At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.
About The Role
Altera is at the forefront of programmable logic and hardware acceleration. Our mission is to empower developers and system architects to rapidly design and deploy next-generation systems using advanced FPGA and SoC technologies.
Within Altera, the High-Level Synthesis (HLS) team builds cutting-edge compiler systems that bridge the gap between software and hardware. We transform high-level programming models into highly optimized hardware implementations, enabling breakthroughs in AI, cloud infrastructure, and domain-specific acceleration.
We are looking for talent who are excited to push the boundaries of compilers, systems, and hardware/software co-design.
What You’ll Work On
As a member of the HLS research and engineering team, you will contribute to both production compiler systems and forward-looking research:
Design and develop next-generation compiler infrastructure for HLS
Invent and implement novel compiler passes, optimizations, and code transformations for hardware synthesis
Explore advanced compilation techniques for AI/ML workloads, including graph-level and system-level optimizations
Improve end-to-end compilation flow from C/C++ (and beyond) to RTL, focusing on performance, power, and area efficiency
Prototype and evaluate new ideas in collaboration with research and product teams
Contribute to publications, patents, and internal technical innovations
Work closely with hardware architects and domain experts to co-design future acceleration platforms
What We Offer
A collaborative environment where research ideas turn into shipped products
Competitive compensation and benefits
Opportunities for career growth in both research and engineering tracks
A culture that values innovation, ownership, and technical excellence
Salary
The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$133.2K - $192.8K USD
We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.
#CG-1
Qualifications
Minimum Qualifications
Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field, with 3+ years of experience
Strong foundation in one or more of the following:
Compiler design (e.g., optimization, IR design, code generation)
Programming languages or systems
Computer architecture or digital design
Proficiency in C/C++ or similar systems programming languages
Preferred Qualifications
Research experience in compilers, HLS, or hardware/software co-design
Familiarity with LLVM, MLIR, or similar compiler infrastructures
Exposure to FPGA/ASIC design flows or hardware description languages (Verilog/VHDL)
Background in optimizing AI/ML workloads or domain-specific accelerators
Publications in relevant conferences or demonstrated research impact
Job Type
Regular
Shift
Shift 1 (United States of America)
Primary Location:
San Jose, California, United States
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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