Hardware Engineer Mid.

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Summary
The Ash Group is hiring a Hardware Engineer (24549) for our client, a global technology distributor connecting leading manufacturers of electronic components and computing solutions. This is a 12-month contract position working in Mountain View, CA (Onsite). We are offering a pay rate up to $66 per hour W2 based on skill set.
Role Details
Compensation: $66/hr W2
Benefits: Medical, dental, vision, and direct primary care benefits. After six months of employment, enjoy a 4% matched 401(k) plan with immediate 100% vesting.
Duration: 12-months
Location: Mountain View, CA (Onsite)

Mid-level hardware engineer responsible for developing C/C++ test content, firmware, and FPGA prototypes, driving post‑silicon bring‑up and validation, and collaborating across design, firmware, and validation teams to ensure silicon readiness.

Key Responsibilities
Develop C and C++ test content, low‑level drivers, and firmware for subsystem and SoC verification.
Extend compile and build flows to support custom firmware‑style tests.
Own the FPGA prototyping platform, creating board images, bit files, and custom RTL.
Build and maintain Python tooling to interface with the FPGA platform.
Debug FPGA and post‑silicon issues using JTAG, logic analyzers, oscilloscopes, and multimeters.
Drive post‑silicon bring‑up, run validation suites, and meet exit criteria on schedule.
Root‑cause post‑silicon test failures, analyze scan dumps, coordinate cross‑team debugging, and deliver fixes.

Qualifications
Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
7+ years of relevant experience in hardware verification and post‑silicon validation.
Proven experience developing C/C++ test content for subsystem and SoC verification, including bare‑metal and firmware‑style tests.
Hands‑on experience with FPGA prototyping or emulation platforms such as HAPS or Xilinx.
Proficiency in hardware debug using JTAG, logic analyzers, oscilloscopes, and multimeters.
Experience with post‑silicon verification of IP, subsystems, or SoCs, including test planning, development, failure debug, and coverage signoff.
Strong Python scripting skills for test automation, build flows, and data parsing.
In‑depth knowledge of verification principles, testbench architecture, and stimulus generation, with a track record of debugging complex designs.
Familiarity with industry protocols such as AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, and USB.
Strong communication skills and ability to collaborate across architecture, design, firmware, and validation teams.
Solid understanding of silicon and/or computer architecture.
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