U
Hardware Design Engineer
Accepting applicationsUST · Hyderabad, Telangana, India
Full-Time Mid FPGAVLSIVerilogperlpython
Estimated market salary
₹19-30 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
6d ago
Category
Design
Experience
Mid
Country
India
Role Description
UST Job Title: Technical Lead I - VLSI
Who We Are
At UST, we help the world s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in over 25 countries, we build for boundless impact touching billions of lives in the process. Visit us at UST.com.
Job Description
Required skill for the Job:
Basic STA knowledge along with tools like Vivado.
Experience on FPGA platforms like AMD(XILINX)/Altera.
Expertise in digital hardware designing using Verilog on large AMD(Xilinx)/altera FPGAs
Experience in scripting language like perl, python and tcl
Working experience on Linux. Ensure to complete design and timing verification tasks within allotted timelines.
Ability to work individually and in a teamBasic
Job Deliverable
Design, implementation, test, integration, and delivery of system level digital designs for FPGA blocks timing verification Perform task of debugging design timing related issues on different FPGA families Perform the work of manifold segmentation of the FPGA designs. Run internal scripts for performance testing and update scripts when necessary Education
Qualification
BTech/MTech Experience Level: 4+ years
What We Believe
We re proud to embrace the same values that have shaped UST since the beginning. Since day one, we ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do.
Humility
We will listen, learn, be empathetic and help selflessly in our interactions with everyone.
Humanity
Through business, we will better the lives of those less fortunate than ourselves.
Integrity
We honour our commitments and act with responsibility in all our relationships.
Equal Employment Opportunity Statement
UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.
All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.
UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.
To support and promote the values of UST.
Comply with all Company policies and procedures
Skills
vlsi design,digital hardware designing,verilog,perl,python,
Show more Show less
UST Job Title: Technical Lead I - VLSI
Who We Are
At UST, we help the world s best organizations grow and succeed through transformation. Bringing together the right talent, tools, and ideas, we work with our client to co-create lasting change. Together, with over 30,000 employees in over 25 countries, we build for boundless impact touching billions of lives in the process. Visit us at UST.com.
Job Description
Required skill for the Job:
Basic STA knowledge along with tools like Vivado.
Experience on FPGA platforms like AMD(XILINX)/Altera.
Expertise in digital hardware designing using Verilog on large AMD(Xilinx)/altera FPGAs
Experience in scripting language like perl, python and tcl
Working experience on Linux. Ensure to complete design and timing verification tasks within allotted timelines.
Ability to work individually and in a teamBasic
Job Deliverable
Design, implementation, test, integration, and delivery of system level digital designs for FPGA blocks timing verification Perform task of debugging design timing related issues on different FPGA families Perform the work of manifold segmentation of the FPGA designs. Run internal scripts for performance testing and update scripts when necessary Education
Qualification
BTech/MTech Experience Level: 4+ years
What We Believe
We re proud to embrace the same values that have shaped UST since the beginning. Since day one, we ve been building enduring relationships and a culture of integrity. And today, it's those same values that are inspiring us to encourage innovation from everyone, to champion diversity and inclusion and to place people at the centre of everything we do.
Humility
We will listen, learn, be empathetic and help selflessly in our interactions with everyone.
Humanity
Through business, we will better the lives of those less fortunate than ourselves.
Integrity
We honour our commitments and act with responsibility in all our relationships.
Equal Employment Opportunity Statement
UST is an Equal Opportunity Employer. We believe that no one should be discriminated against because of their differences, such as age, disability, ethnicity, gender, gender identity and expression, religion, or sexual orientation.
All employment decisions shall be made without regard to age, race, creed, colour, religion, sex, national origin, ancestry, disability status, veteran status, sexual orientation, gender identity or expression, genetic information, marital status, citizenship status or any other basis as protected by federal, state, or local law.
UST reserves the right to periodically redefine your roles and responsibilities based on the requirements of the organization and/or your performance.
To support and promote the values of UST.
Comply with all Company policies and procedures
Skills
vlsi design,digital hardware designing,verilog,perl,python,
Show more Show less
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