TI
Hardware Design Engineer
Accepting applicationsTrilyon, Inc. · Boxborough, MA
Contract Mid_senior AIAnalogC++DDRMachine Learning
Posted
19h ago
Category
Design
Experience
Mid_senior
Country
United States
For over 16 years, Trilyon has been at the forefront of providing comprehensive global workforce solutions and staffing services. Leveraging our extensive expertise across multiple domains such as Cloud technology, Salesforce, AI, Machine Learning, and Technical Writing, we consistently exceed expectations in catering to a wide range of requirements.
Currently we are seeking a “Hardware Design Engineer 2” for one of our clients that is a leading multination corporation.
Position: Hardware Design Engineer 2
Location: 90 Central Street, Boxborough, MA 017199 (Hybrid)
Duration: 12 months contract
Job Description:
The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
RTL design for memory I/O
PHY Digital Architecture development from pathfinding, coding, verification to physical implementation
PHY link layer design, implementation & verification with Analog and System architect.
PHY Analog/Digital co-design
Digital design and RTL coding
Timing Synthesis & Drive Physical implementation
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the unit tests
Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues
PREFERRED EXPERIENCE:
Digital design engineering experience
Experienced with Verilog, System Verilog, C, and C++
Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus
Knowledge of clocking architectures, synchronization, and CDC methodology
Experience with synthesis, Timing closure
SERDES, DDR, Memory Controller, or MAC Design experience is preferred
Proficient in debugging firmware and RTL code using simulation tools
Strong understanding of computer organization/architecture.
Mixed signal RTL, Low power design experience is a plus
Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS:
Bachelors or Master’s degree in computer engineering/Electrical Engineering
Equal Employment Opportunity
Trilyon is an Equal Opportunity Employer, committed to fairness and respect for all individuals. We value diversity in age, disability, ethnicity, gender, gender identity, religion, and sexual orientation, believing it drives innovation and better service. Employment decisions are made impartially, without regard to any protected characteristic under federal, state, or local law. Our diverse team drives innovation, competitiveness, and creativity, enhancing our ability to effectively serve our clients and communities. This commitment to diversity makes us stronger and more adaptable.
Warm Regards,
Signature
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Currently we are seeking a “Hardware Design Engineer 2” for one of our clients that is a leading multination corporation.
Position: Hardware Design Engineer 2
Location: 90 Central Street, Boxborough, MA 017199 (Hybrid)
Duration: 12 months contract
Job Description:
The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
RTL design for memory I/O
PHY Digital Architecture development from pathfinding, coding, verification to physical implementation
PHY link layer design, implementation & verification with Analog and System architect.
PHY Analog/Digital co-design
Digital design and RTL coding
Timing Synthesis & Drive Physical implementation
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the unit tests
Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues
PREFERRED EXPERIENCE:
Digital design engineering experience
Experienced with Verilog, System Verilog, C, and C++
Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus
Knowledge of clocking architectures, synchronization, and CDC methodology
Experience with synthesis, Timing closure
SERDES, DDR, Memory Controller, or MAC Design experience is preferred
Proficient in debugging firmware and RTL code using simulation tools
Strong understanding of computer organization/architecture.
Mixed signal RTL, Low power design experience is a plus
Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS:
Bachelors or Master’s degree in computer engineering/Electrical Engineering
Equal Employment Opportunity
Trilyon is an Equal Opportunity Employer, committed to fairness and respect for all individuals. We value diversity in age, disability, ethnicity, gender, gender identity, religion, and sexual orientation, believing it drives innovation and better service. Employment decisions are made impartially, without regard to any protected characteristic under federal, state, or local law. Our diverse team drives innovation, competitiveness, and creativity, enhancing our ability to effectively serve our clients and communities. This commitment to diversity makes us stronger and more adaptable.
Warm Regards,
Signature
Show more Show less