Hardware Design Engineer (ASIC/FPGA)

A leading global trading firm is hiring a Hardware Engineer to join its Global Hardware group and help build the next generation of proprietary ASICs behind the firm's trading infrastructure.
Within the Global Hardware organization, you'll take on multi-year, high-leverage engineering problems that shape the speed and scalability of the firm's trading platforms. The group builds in-house silicon that creates real, measurable edge in latency-critical environments, working shoulder to shoulder with software engineers, researchers, and trading desks on genuinely hard technical problems.

The position blends hardware design, verification, and system-level reasoning. You'll be involved across the whole ASIC lifecycle, from RTL authoring and validation through to integration into wider hardware platforms. Because the team is deliberately lean and highly collaborative, engineers get wide ownership and visibility across the design process instead of being boxed into one narrow specialism.

What You'll Do

ASIC Design & Development
Work across the entire ASIC lifecycle, from initial specification through integration and rollout
Write and implement RTL for next-generation ASIC platforms in SystemVerilog
Weigh in on architecture and design decisions for performance-critical hardware
Build new capability that keeps pace with changing trading and infrastructure demands
Partner with hardware, software, and research groups to turn requirements into scalable designs
Verification & Testing
Build unit tests and verification environments for RTL designs
Validate the behavior and performance of hardware blocks
Root-cause design and integration issues throughout development
Help shape verification methodology and testing infrastructure
Make sure designs hold up on reliability, performance, and maintainability
Engineering & Tooling
Write scripts and tooling that make engineering workflows faster
Push forward automation across design and verification
Keep improving development methodology and day-to-day engineering practice

What You Bring
BS or above in Electrical Engineering, Computer Engineering, Computer Science, or a comparable technical field
Deep hands-on experience with RTL design and development in SystemVerilog
Firm grasp of digital design fundamentals
Working ability in C++
Track record building and running verification and test strategies
Exposure to multi-clock-domain designs and clock-domain crossing
Sound understanding of Ethernet protocols and core networking concepts
Scripting experience in Python, Bash, or similar
Sharp debugging and problem-solving instincts
Comfortable collaborating across different engineering disciplines
Nice to Have
Prior ASIC development experience
FPGA development background with relevant ASIC design exposure
Familiarity with PMA (Physical Media Attachment) technologies
Experience with high-performance networking systems
Background in low-latency or performance-sensitive system design
Time spent in trading, market infrastructure, or fintech environments
Experience building verification frameworks or test automation tooling
Strong C++ development ability

What Success Looks Like
Moves comfortably between architecture-level thinking and hands-on build
Genuinely enjoys hard technical problems that straddle hardware and software
Owns systems end to end and sees them through from design to deployment
Brings real rigor and attention to detail
Works well in a collaborative, cross-team setting
Picks things up fast and adapts as the technical landscape shifts
Explains complex work clearly to technical and non-technical audiences alike
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