GLS Verification Lead

Job Title: GLS Lead Engineers
Experience: 7+yrs
Location: Bangalore
Job Type: Full-time
Industry: Semiconductors / VLSI /STA Engineers


Job Responsibilitie
sLead Gate Level Simulation (GLS) activities for SoC/IP verification programs
.Develop and execute GLS test plans for functional and timing validation
.Debug GLS failures related to timing, reset, initialization, X-propagation, and CDC issues
.Work closely with RTL, DFT, STA, PD, and Verification teams to resolve issues
.Analyze SDF annotation, setup/hold violations, and simulation mismatches
.Automate GLS regression flows and improve verification efficiency
.Support power-aware GLS and low-power verification activities
.Drive closure of GLS signoff before tape-out
.Required Skill
sStrong experience in Gate Level Simulation (GLS) and timing simulations
.Good understanding of Verilog/SystemVerilog
.Experience with VCS/Xcelium/Questa simulators
.Knowledge of SDF back-annotation, STA concepts, and CDC/RDC
.Experience in debugging waveform issues using Verdi/DVE
.Scripting knowledge in Perl/Python/Shell/TCL
.Understanding of SoC architecture and ASIC design flow
.Preferred Skill
sExperience with low-power verification (UPF/CPF)
.Exposure to DFT and scan validation
.Knowledge of emulation/prototyping is an added advantage
.Educatio
nB.E/B.Tech/M.E/M.Tech in Electronics/ECE/EEE or related field

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Interested can share CV to sharmila.b@acldigital.c

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