LI
Full Time Lead DFT Engineer
Accepting applicationsLanceSoft, Inc. · Santa Clara, CA
Full-Time Mid_senior ATPGDFTMentorRTLSoC
Posted
4d ago
Category
Test
Experience
Mid_senior
Country
United States
Job Title - Full Time Lead DFT Engineer
Experience Range - 12+ years
Job Location - Santa Clara-CA
Job Description -
SoC DFT Lead with experience to define, architect, and execute Design-for-Test solutions for complex multi-partition SoCs from RTL through silicon bring-up. The successful candidate will lead a team of DFT engineers and work closely with RTL, Physical Design, Validation, and Post-Silicon teams to ensure high-quality test implementation and coverage across the entire chip.
Key Responsibilities
• Define and document SoC-level DFT architecture and implementation strategy.
• Lead DFT execution across block, partition, and top-level integration.
• Architect and implement scan, scan compression, MBIST, LBIST, boundary scan, SSN, and iJTAG solutions.
• Plan and manage DFT requirements, schedules, netlist releases, and execution milestones.
• Coordinate with RTL, Physical Design, Timing, and Validation teams throughout the design cycle.
• Drive DFT insertion, verification, ATPG generation, fault coverage closure, and pattern signoff.
• Lead DFT structure verification, gate-level simulations, logic equivalence checks, and pattern retargeting activities.
• Analyze test coverage, diagnose failures, and support silicon bring-up and production ramp.
• Mentor and guide DFT engineers and provide technical leadership across projects.
• Participate in design reviews and ensure DFT readiness at all project milestones.
Required Qualifications
• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of experience in DFT with proven leadership of large SoC programs.
• Strong expertise in scan insertion, scan compression, ATPG, MBIST, LBIST, boundary scan, and gate-level simulation.
Show more Show less
Experience Range - 12+ years
Job Location - Santa Clara-CA
Job Description -
SoC DFT Lead with experience to define, architect, and execute Design-for-Test solutions for complex multi-partition SoCs from RTL through silicon bring-up. The successful candidate will lead a team of DFT engineers and work closely with RTL, Physical Design, Validation, and Post-Silicon teams to ensure high-quality test implementation and coverage across the entire chip.
Key Responsibilities
• Define and document SoC-level DFT architecture and implementation strategy.
• Lead DFT execution across block, partition, and top-level integration.
• Architect and implement scan, scan compression, MBIST, LBIST, boundary scan, SSN, and iJTAG solutions.
• Plan and manage DFT requirements, schedules, netlist releases, and execution milestones.
• Coordinate with RTL, Physical Design, Timing, and Validation teams throughout the design cycle.
• Drive DFT insertion, verification, ATPG generation, fault coverage closure, and pattern signoff.
• Lead DFT structure verification, gate-level simulations, logic equivalence checks, and pattern retargeting activities.
• Analyze test coverage, diagnose failures, and support silicon bring-up and production ramp.
• Mentor and guide DFT engineers and provide technical leadership across projects.
• Participate in design reviews and ensure DFT readiness at all project milestones.
Required Qualifications
• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of experience in DFT with proven leadership of large SoC programs.
• Strong expertise in scan insertion, scan compression, ATPG, MBIST, LBIST, boundary scan, and gate-level simulation.
Show more Show less