MT
Front End RTL Design Lead
Accepting applicationsMulya Technologies · Greater Bengaluru Area
Full-Time Mid_senior RTL DesignVerilogSystemVerilogSynthesisSoC
Estimated market salary
₹21-38 LPA
This is a SiliconBoard market estimate, not an employer-posted salary.
Posted
19h ago
Category
Design
Experience
Mid_senior
Country
India
Front End RTL Design Lead
Among. The top 4 IT companies, in India ranked by market capitalization and revenue
Bangalore
Front End RTL Design Lead
•Responsibility for RTL design requirements for the SOC designs having multiple processing subsystems, NOC, interface subsystems
•Work with architecture team to develop RTL meeting design specifications and requirements
•Perform RTL synthesis to meet area and performance targets
•Debug and resolve RTL design issues and work with DV team to achieve high level of design quality
•Ensure all the commitments for front end are met for RTL development in committed timeline and quality
•Experience in major SOC design architectures – ARM, RISC-V, in variety of appl domains
10-15 Years experience
Prefer experience in managing several SOC developments
Proficiency in VDHL and Verilog
Experience in SOC design flow
Understanding SOC architecture
Masters minimum education
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"
Show more Show less
Among. The top 4 IT companies, in India ranked by market capitalization and revenue
Bangalore
Front End RTL Design Lead
•Responsibility for RTL design requirements for the SOC designs having multiple processing subsystems, NOC, interface subsystems
•Work with architecture team to develop RTL meeting design specifications and requirements
•Perform RTL synthesis to meet area and performance targets
•Debug and resolve RTL design issues and work with DV team to achieve high level of design quality
•Ensure all the commitments for front end are met for RTL development in committed timeline and quality
•Experience in major SOC design architectures – ARM, RISC-V, in variety of appl domains
10-15 Years experience
Prefer experience in managing several SOC developments
Proficiency in VDHL and Verilog
Experience in SOC design flow
Understanding SOC architecture
Masters minimum education
Contact
Uday
muday_bhaskar@yahoo.com
Mulya Technologies
"Mining the Knowledge Community"
Show more Show less