AD
FPGA Verification Engineer
Accepting applicationsACL Digital · El Segundo, CA
Contract Mid_senior ASICFPGASystemVerilogUVMVerilog
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Role: ASIC / FPGA Verification Engineer
Location: El Segundo, CA
Type: Contract
Duration: 12 Months
Pay Rate: $84/hr - $100/hr on W2
This is a hybrid role - 1 day onsite per week
Position Responsibilities:
Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.
Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming principles such as Inheritance and Polymorphism, while utilizing UVM to build drivers, monitors, predictors, and scoreboards.
Create Functional Coverage Models and conduct Code Coverage analysis to ensure thorough verification of designs during simulation.
Set up regression tests and collect coverage metrics to ensure comprehensive verification and track progress over time.
Assist in FPGA-based prototyping and validation based on program and system requirements and complexity.
Collaborate with cross-functional teams to ensure that verification strategies align with overall project goals and timelines.
Required Skills:
Proven experience in ASIC/FPGA verification processes
Familiarity with defining the architectural framework for ASIC/FPGA verification using SystemVerilog/UVM, including the delivery and release of production designs
Proficiency in hardware verification languages, particularly SystemVerilog and SystemVerilog Assertions
Demonstrated experience in implementing test plans effectively
Solid understanding of Object-Oriented Programming principles, such as Inheritance and Polymorphism
Capability to design self-checking and reusable testbenches from the ground up
Experience in developing Functional Coverage Models and achieving Code Coverage closure
Capable of collaborating with design and system engineering to establish accurate and verifiable ASIC/FPGA level specifications
Familiarity with waveform debug tools
Best Regards,
Rupesh Kumar
Lead –Team Talent Acquisition
ALTEN Calsoft Labs
2890 Zanker Road, Suite 200, San Jose, CA 95134
D : +1 408-755-3056
E: rupesh.k@acldigital.com
FOLLOW US @ Twitter | Linkedin | Facebook | www.Acldigital.com
Show more Show less
Location: El Segundo, CA
Type: Contract
Duration: 12 Months
Pay Rate: $84/hr - $100/hr on W2
This is a hybrid role - 1 day onsite per week
Position Responsibilities:
Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog.
Develop self-checking and reusable test benches from the ground up, employing Object-Oriented Programming principles such as Inheritance and Polymorphism, while utilizing UVM to build drivers, monitors, predictors, and scoreboards.
Create Functional Coverage Models and conduct Code Coverage analysis to ensure thorough verification of designs during simulation.
Set up regression tests and collect coverage metrics to ensure comprehensive verification and track progress over time.
Assist in FPGA-based prototyping and validation based on program and system requirements and complexity.
Collaborate with cross-functional teams to ensure that verification strategies align with overall project goals and timelines.
Required Skills:
Proven experience in ASIC/FPGA verification processes
Familiarity with defining the architectural framework for ASIC/FPGA verification using SystemVerilog/UVM, including the delivery and release of production designs
Proficiency in hardware verification languages, particularly SystemVerilog and SystemVerilog Assertions
Demonstrated experience in implementing test plans effectively
Solid understanding of Object-Oriented Programming principles, such as Inheritance and Polymorphism
Capability to design self-checking and reusable testbenches from the ground up
Experience in developing Functional Coverage Models and achieving Code Coverage closure
Capable of collaborating with design and system engineering to establish accurate and verifiable ASIC/FPGA level specifications
Familiarity with waveform debug tools
Best Regards,
Rupesh Kumar
Lead –Team Talent Acquisition
ALTEN Calsoft Labs
2890 Zanker Road, Suite 200, San Jose, CA 95134
D : +1 408-755-3056
E: rupesh.k@acldigital.com
FOLLOW US @ Twitter | Linkedin | Facebook | www.Acldigital.com
Show more Show less