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FPGA SW Validation Engineer
Accepting applicationsAltera · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICEthernetFPGAPCIePerl
Posted
4d ago
Category
Design
Experience
Mid_senior
Country
India
Job Details
Job Description:
Validates and researches the Compiler optimizations, Partial Reconfiguration (PR) flow, Debugging features like SignalTap & System Console, etc. using
Quartus Design Software and Altera FPGA Hardware.
Creates designs using HDLs and Altera IPs and verifies them for functionality and timing on Altera FPGA Hardware Boards.
Regresses the designs during each release for QoR, and monitors performance over the targeted FPGA devkits to assess improvements.
Collaborates with cross-functional teams to develop and improve validation strategies for improving Compiler/PR validation and help resolve customer issues as they occur.
Qualifications
Experience : 5+ years of relevant experience in FPGA/ASIC Design, RTL Coding, Verification and HW Debug
Education : Master's/Bachelor's Degree in Electronics/VLSI/Digital Design or other related disciplines
Requirements -
FPGA/Digital Logic Design, RTL design and verification using VHDL, Verilog or SystemVerilog.
Experienced in FPGA Devices like Agilex, Virtex and Tools like Altera Quartus, Xilinx Vivado, Synplify, etc
Good experience in FPGA Partial Reconfiguration (PR) flow, and HW debugging skills using SignalTap or ChipScope
Good experience with Simulation/Verification of digital designs using VCS, Questa, XCelium, STA and Hardware validation of FPGA Designs
Knowledge of Unix/Linux along with Automation, like Shell, Perl/TCL or Python Scripting is required
Knowledge of PCIe, Ethernet, Avalon bus protocols, AHB, AXI, HPS and High-Speed interfaces are essential
Job Type
Regular
Shift
Shift 1 (India)
Primary Location:
Bengaluru, Karnataka, India
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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Job Description:
Validates and researches the Compiler optimizations, Partial Reconfiguration (PR) flow, Debugging features like SignalTap & System Console, etc. using
Quartus Design Software and Altera FPGA Hardware.
Creates designs using HDLs and Altera IPs and verifies them for functionality and timing on Altera FPGA Hardware Boards.
Regresses the designs during each release for QoR, and monitors performance over the targeted FPGA devkits to assess improvements.
Collaborates with cross-functional teams to develop and improve validation strategies for improving Compiler/PR validation and help resolve customer issues as they occur.
Qualifications
Experience : 5+ years of relevant experience in FPGA/ASIC Design, RTL Coding, Verification and HW Debug
Education : Master's/Bachelor's Degree in Electronics/VLSI/Digital Design or other related disciplines
Requirements -
FPGA/Digital Logic Design, RTL design and verification using VHDL, Verilog or SystemVerilog.
Experienced in FPGA Devices like Agilex, Virtex and Tools like Altera Quartus, Xilinx Vivado, Synplify, etc
Good experience in FPGA Partial Reconfiguration (PR) flow, and HW debugging skills using SignalTap or ChipScope
Good experience with Simulation/Verification of digital designs using VCS, Questa, XCelium, STA and Hardware validation of FPGA Designs
Knowledge of Unix/Linux along with Automation, like Shell, Perl/TCL or Python Scripting is required
Knowledge of PCIe, Ethernet, Avalon bus protocols, AHB, AXI, HPS and High-Speed interfaces are essential
Job Type
Regular
Shift
Shift 1 (India)
Primary Location:
Bengaluru, Karnataka, India
Additional Locations:
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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