LT
FPGA / RTL Design Engineer
Accepting applicationsL&T Technology Services · Bengaluru, Karnataka, India
Full-Time Mid_senior FPGAPCIeRTLSERDESSystemVerilog
Posted
21h ago
Category
Design
Experience
Mid_senior
Country
India
FPGA / RTL Design Engineer
Role Overview
We are looking for an experienced FPGA/RTL Design Engineer to design, develop, and validate FPGA-based digital systems. The ideal candidate will have strong expertise in RTL design, FPGA implementation, timing closure, and high-speed interface integration, along with hands-on experience in simulation, debugging, and optimization.
Key Responsibilities
Develop and implement RTL designs using Verilog, VHDL, or SystemVerilog.
Design and integrate FPGA-based solutions, IP blocks, and system-level components.
Perform functional simulation, verification, and debugging of FPGA designs.
Execute synthesis, static timing analysis (STA), and timing closure activities.
Troubleshoot and resolve design, performance, and integration issues.
Collaborate with cross-functional teams to deliver optimized and scalable FPGA solutions.
Support customer engagements and contribute to technical collateral and reusable assets.
Required Qualifications
Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
5+ years of experience in FPGA design, RTL development, or FPGA applications engineering.
Strong expertise in Verilog, VHDL, and/or SystemVerilog.
Hands-on experience with FPGA toolchains such as Xilinx Vivado and/or Intel Quartus.
Experience with third-party simulation and verification tools.
Strong debugging skills with FPGA development boards and lab validation.
Technical Skills
FPGA & RTL Design
RTL design and implementation
FPGA architecture and development
Functional simulation and verification
Synthesis, STA, and timing closure
Signal Processing
FFT (Fast Fourier Transform)
FIR Filters
CORDIC Algorithms
Image & Video Processing
MIPI Interfaces
Video Processing Pipelines
ISP (Image Signal Processing)
High-Speed Interfaces
PCIe
JESD204B
SERDES
Preferred Skills
Experience with FPGA-based prototyping and hardware validation.
Strong understanding of digital design concepts and system architecture.
Ability to debug complex hardware and integration issues.
Excellent problem-solving and communication skills.
Experience: 5+ Years
Skill Set: FPGA, RTL Design, Verilog, VHDL, SystemVerilog, Vivado, Quartus, STA, PCIe, JESD204B, SERDES, Signal Processing, Image Processing.
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Role Overview
We are looking for an experienced FPGA/RTL Design Engineer to design, develop, and validate FPGA-based digital systems. The ideal candidate will have strong expertise in RTL design, FPGA implementation, timing closure, and high-speed interface integration, along with hands-on experience in simulation, debugging, and optimization.
Key Responsibilities
Develop and implement RTL designs using Verilog, VHDL, or SystemVerilog.
Design and integrate FPGA-based solutions, IP blocks, and system-level components.
Perform functional simulation, verification, and debugging of FPGA designs.
Execute synthesis, static timing analysis (STA), and timing closure activities.
Troubleshoot and resolve design, performance, and integration issues.
Collaborate with cross-functional teams to deliver optimized and scalable FPGA solutions.
Support customer engagements and contribute to technical collateral and reusable assets.
Required Qualifications
Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
5+ years of experience in FPGA design, RTL development, or FPGA applications engineering.
Strong expertise in Verilog, VHDL, and/or SystemVerilog.
Hands-on experience with FPGA toolchains such as Xilinx Vivado and/or Intel Quartus.
Experience with third-party simulation and verification tools.
Strong debugging skills with FPGA development boards and lab validation.
Technical Skills
FPGA & RTL Design
RTL design and implementation
FPGA architecture and development
Functional simulation and verification
Synthesis, STA, and timing closure
Signal Processing
FFT (Fast Fourier Transform)
FIR Filters
CORDIC Algorithms
Image & Video Processing
MIPI Interfaces
Video Processing Pipelines
ISP (Image Signal Processing)
High-Speed Interfaces
PCIe
JESD204B
SERDES
Preferred Skills
Experience with FPGA-based prototyping and hardware validation.
Strong understanding of digital design concepts and system architecture.
Ability to debug complex hardware and integration issues.
Excellent problem-solving and communication skills.
Experience: 5+ Years
Skill Set: FPGA, RTL Design, Verilog, VHDL, SystemVerilog, Vivado, Quartus, STA, PCIe, JESD204B, SERDES, Signal Processing, Image Processing.
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