FPGA Digital Design and Verification Engineer-Contract

Job Details

Job Description:

Altera is seeking a highly motivated FPGA Digital Design and Verification Engineer-Contract. This 6 month ACE contract provides hands-on experience working on industry-leading programmable logic devices, SoC platforms, and verification environments. The role is ideal for candidates eager to grow their expertise in RISC-V design, SystemVerilog, UVM-based verification, and digital design methodologies.

You will collaborate with experienced engineers to design, verify, and validate RTL blocks and system-level features used in next-generation FPGA products.

Key Responsibilities

RISC-V design
Develop and maintain SystemVerilog/UVM-based verification environments for FPGA IPs and subsystems
Create self-checking testbenches, constrained-random tests, and functional coverage models
Write and debug SystemVerilog Assertions (SVA) to ensure protocol and design correctness
Execute and analyze simulations using industry-standard EDA tools (VCS, QuestaSim, ModelSim)
Assist in debugging RTL and verification failures, working closely with design engineers
Verify common communication protocols (e.g., UART, SPI) and custom interconnects
Contribute to documentation of verification plans, test strategies, and results
Support FPGA-based systems including AI/ML accelerators, memory interfaces, and SoC components

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$100-105K USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Qualifications

Required Qualifications

Bachelor’s Degree in Computer or Electrical Engineering or related field
1+ years' experience in Digital Logic Design and Computer Architecture
RISC-V and digital design experience
Proficiency in SystemVerilog and Verilog
Knowledge of UVM, functional coverage, constrained random verification, and assertions
Experience using simulation and verification tools such as ModelSim, QuestaSim, or Synopsys VCS
Familiarity with Linux-based development environments
Ability to debug simulation issues and analyze waveforms effectively

Preferred Qualifications

Experience verifying communication protocols (UART, SPI, AXI preferred)
Exposure to FPGA tools such as Intel Quartus Prime or Xilinx Vivado
Knowledge of SVA or formal verification concepts
Programming or scripting experience in Python, Perl, Tcl, or C
Exposure to HLS, SoC design, or hardware acceleration for AI/ML workloads

Job Type

Contract Employee (Fixed Term)

Shift

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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