FPGA Developer ( Lead )

Job Description

As the FPGA Lead you'll own the greenfield implementation: architecting and building the RTL that moves market data and orders in nanoseconds, setting the design and verification standards the team will work to, and deciding where to lean on existing IP versus building from scratch. This is a hands-on role where design choices translate directly into trading edge. What you'll do

Own the FPGA architecture for latency-critical trading paths (market data ingest, order entry, host interface).
Write and optimize production RTL, then drive it to timing closure on the latest AMD/Xilinx devices.
Set RTL, verification, and resource-management standards for a growing FPGA team.
Make build-vs-buy decisions on IP, and integrate or replace existing cores as needed.
Work directly with trading, quant, and infra teams to turn latency requirements into hardware. Must have
7+ years in FPGA development, with deep hands-on RTL in Verilog/SystemVerilog.
Demonstrated ownership of shipped designs (written from scratch, not just maintained) in at least two of: network packet processing (PCS, MAC, UDP, TCP/IP), high-speed Ethernet, PCI Express, memory interfaces.
Proven timing closure on complex designs, plus strong resource management and latency optimization.
Fluency with simulation and toolchains: Vivado, Vitis, ModelSim/Questa or Xilinx simulator.
Solid modern C and Python for tooling, host-side integration, and automation. Nice to have
Experience on current-gen Xilinx architectures (UltraScale+, Versal).
Cryptographic cores / accelerators.
Low-latency networking or trading-systems background.

Required Skills

['Verilog/VHDL']

Additional Information

7+ years in FPGA development, with deep hands-on RTL in Verilog/SystemVerilog.

Demonstrated ownership of shipped designs (written from scratch, not just maintained) in at least two of: network packet processing (PCS, MAC, UDP, TCP/IP), high-speed Ethernet, PCI Express, memory interfaces.
Proven timing closure on complex designs, plus strong resource management and latency optimization.
Fluency with simulation and toolchains: Vivado, Vitis, ModelSim/Questa or Xilinx simulator.
Solid modern C and Python for tooling, host-side integration, and automation.
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