Founding ASIC / SoC Design Verification Engineer

ChipSage Labs is building agentic solutions for chip design teams in the semiconductor industry. We are a well-funded & early-stage team of EDA/AI engineers and researchers developing agentic tools designed to support chip design and verification workflows.

About the Role
We are seeking a highly motivated and experienced ASIC / SoC Design Verification Engineer to help build next-generation AI-driven chip design and verification workflows. You will play a critical role in developing scalable verification environments, comprehensive DV infrastructures, and advanced debugging methodologies for complex hardware IPs and SoC subsystems. We are

This role involves close collaboration with the founding team on cutting-edge verification systems, AI-assisted workflows, and next-generation engineering automation platforms.
The ideal candidate should have strong expertise in SystemVerilog, UVM, constrained-random verification, assertion-based verification, regression infrastructure, waveform debugging, and coverage-driven methodologies. Candidates should have experience verifying complex and high-performance IPs such as LPDDR/DDR, PCIe, NVLINK, AI accelerators, processors, NoCs, interconnects, cache coherency systems, security IPs, or protocol subsystems.

Responsibilities
Own the verification of hardware IPs, subsystems, or SoC-level components across advanced chip design projects and internal research platforms
Develop scalable and reusable UVM verification environments including scoreboards, monitors, assertions, constrained-random infrastructures, smoke tests, regression suites, and coverage closure frameworks
Build and maintain robust regression and debugging infrastructures supporting large-scale verification workflows and rapid iteration cycles
Drive bug triage, root-cause analysis, waveform debugging, protocol-level debugging, and simulation failure analysis
Collaborate closely with RTL, architecture, infrastructure, and AI engineering teams
Contribute to AI-assisted verification methodologies, automated regression orchestration systems, waveform analysis automation, and LLM-assisted verification workflows
Help shape verification architecture decisions, engineering tooling, and long-term DV infrastructure strategy

Qualifications
PhD or MS in EE/CS/CE, 3+ years of experience in ASIC / SoC Design Verification
Strong expertise in SystemVerilog, UVM, constrained-random verification, assertions, functional coverage, code coverage, and modern DV methodologies
Hands-on experience with Synopsys and/or Cadence EDA tools including VCS, Verdi, Xcelium, DVE, SimVision, and modern simulation/debug infrastructures
Strong debugging and root-cause analysis skills including deep waveform analysis, regression triage, protocol debugging, and assertion-level debugging
Experience automating verification workflows using Python, Bash, Tcl, Perl, Makefiles, CI/CD-integrated scripting frameworks, or infrastructure automation tooling
Strong understanding of computer architecture concepts including memory systems, cache coherency, interconnects, AI accelerators, or high-performance compute architectures

Preferred Qualifications
Experience as a Chip Lead or led teams through Spec-Tapeout cycles
Experience with formal verification, emulation, or performance modeling
Familiarity with AI-assisted verification flows and verification automation systems
Experience building scalable verification infrastructure for complex SoCs or accelerators
Exposure to AI hardware, security IPs, cache coherency systems, or high-speed protocols

What We’re Looking For
Strong ownership, execution, and problem-solving mindset
Comfortable operating in a fast-paced startup environment
Ability to work independently while collaborating closely with the founding team
Passion for advanced chip design, verification systems, and AI-driven engineering workflows
Strong communication and technical collaboration skills
Show more Show less