Formal Verification Engineer – Verification Engineer

Formal Verification Engineer Verification Engineer 3

Ref ID: 504-1
Location: Bangalore
Work Mode: Onsite / Hybrid (as per project requirement)
Experience: 5 8 Years

Role Overview

We are looking for an experienced Formal Verification Engineer to work on advanced SoC and DDR PHY verification activities. The role involves formal property verification, connectivity verification, and assertion-based verification for complex semiconductor designs.
The candidate will work closely with design, DV, and architecture teams to develop scalable formal verification methodologies and improve overall verification coverage and quality.

Key Responsibilities
Perform formal verification for Test Chips and DDR PHY designs
Execute connectivity verification for test chips and subsystem blocks
Develop and debug SystemVerilog Assertions (SVA) for formal verification
Create and maintain formal verification test plans and coverage models
Build formal verification infrastructure and reusable verification components
Analyze RTL design behavior and identify functional corner cases
Work on block-level and subsystem-level property verification
Use formal verification tools for proof convergence and debug analysis
Collaborate with RTL, DV, and architecture teams during verification closure
Review specifications and convert requirements into formal properties
Support regression execution and failure triage activities
Contribute to methodology improvements for formal verification flows

Required Qualifications
Bachelor s or Master s degree in Electronics, VLSI, Electrical Engineering, or related field
5 - 8 years of experience in semiconductor verification
Strong experience in Formal Verification methodologies
Good understanding of SoC verification concepts and digital design fundamentals
Experience working with DDR PHY or high-speed interface verification is preferred
Technical Skills Formal Verification
Formal Property Verification
Assertion-Based Verification (ABV)
Property Checking
Connectivity Verification
Equivalence Checking
Languages & Methodologies
SystemVerilog
SystemVerilog Assertions (SVA)
Assertion Development
RTL Verification
Tools
Cadence JasperGold
Synopsys VC Formal
Siemens Questa Formal
Formal Verification Debug Tools
Domain Knowledge
SoC Verification
DDR PHY Verification
Digital Design Concepts
Verification Closure Methodologies
Soft Skills
Strong debugging and analytical skills
Good communication and collaboration abilities
Ability to work independently on verification tasks
Structured problem-solving approach
Good documentation and reporting skills

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