Formal verification Engineer

Formal Verification Engineer
About the Role We are seeking a Formal Verification Engineer with deep expertise in FV methodologies and commercial tools to define and drive formal strategies that ensure first-pass silicon success. This role is focused on formal sign-off across complex IP and SoC designs, requiring advanced skills in SystemVerilog Assertions and proof convergence techniques.
Key Responsibilities
Define and execute formal verification strategies for complex IP and SoC designs.
Architect robust, scalable FV environments and deploy reusable UVM/SVA assertion suites.
Collaborate with Architecture and Design teams to translate specifications into comprehensive formal test plans.
Maintain and enhance FV infrastructure, including CI/regression flows and dashboards for sign-off metrics.
Apply advanced formal techniques (assume-guarantee, abstractions, reductions) for efficient bug-hunting and convergence.
Partner with design and verification teams to ensure formal sign-off quality.
Minimum Qualifications
5+ years of experience in ASIC/SoC verification, with at least 3 years focused on formal verification.
Expert-level proficiency with at least one major FV platform: Cadence JasperGold, Synopsys VC Formal, or Mentor Questa Formal.
Strong ability to model complex designs in SystemVerilog and advanced SVA, including cut-points and environment models.
Proven track record of formal sign-off ownership in complex IP or SoC projects.
Preferred Qualifications
Experience with NoCs, cache coherency protocols, and AXI/AMBA.
Background in high-performance design verification.
Familiarity with formal coverage metrics and proof convergence strategies.
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