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Formal Verification Engineer

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Oho Group · San Francisco Bay Area

Full-Time Mid_senior ASICRTLSoCSystemVerilog
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
United States
We are a fast-growing silicon accelerator start-up developing next-generation high-performance compute solutions. We are seeking a motivated Formal Verification Engineer with 1–6 years of industry experience to join our design verification team.

Responsibilities:
Develop and execute formal verification strategies for complex digital designs.
Create assertions, formal test plans, and coverage models.
Collaborate closely with RTL, architecture, and verification teams to ensure design correctness.
Debug and resolve functional issues identified through formal analysis.

Requirements:
B.S., M.S., or Ph.D. in Electrical Engineering, Computer Engineering, or related field.
1–6 years of experience in formal verification of ASIC/SoC designs.
Strong knowledge of SystemVerilog Assertions (SVA) and formal verification methodologies.
Experience with industry-standard formal tools and RTL design/debug flows.
Solid understanding of digital design fundamentals and verification principles.

Join us to help build cutting-edge accelerator technology in a dynamic and collaborative environment.
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