MT
Formal Verification engineer
Accepting applicationsMirafra Technologies · San Francisco Bay Area
Full-Time Mid_senior ASICCadenceDFTMentorPCIe
Posted
2d ago
Category
Verification
Experience
Mid_senior
Country
United States
We are seeking a highly experienced Lead Formal Verification Engineer with over 10 years of expertise in formal methodology, property specification, and advanced verification strategies for complex SoC/ASIC designs. In this role, you will lead formal verification initiatives across high-performance compute, networking, or automotive silicon projects. You will be responsible for setting up formal verification environments from scratch, proving complex control/data path logic, and driving bug hunting and formal proofs for critical IP modules.
Key Responsibilities
Verification Architecture & Strategy: Define and execute end-to-end Formal Verification (FV) strategies for complex IPs, subsystems, and SoC-level control logic.
Formal Environment Setup: Build robust, reusable formal testbenches using industry-standard tools (e.g., Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal).
Property & Assertion Coding: Write high-quality, efficient SystemVerilog Assertions (SVA) and Property Specification Language (PSL) for safety properties, liveness properties, and invariants.
Abstraction & Problem Reduction: Develop advanced formal abstraction techniques (e.g., black-boxing, unrolling, symmetry reduction, case splitting, helper lemmas) to overcome state-space explosion and resolve formal convergence issues.
Coverage & Sign-off: Define formal coverage metrics (bounded proof coverage, core coverage), track verification completeness, and drive formal sign-off for critical blocks.
Formal Applications: Utilize specialized formal apps including Formal Connectivity, Equivalence Checking (LEC/CEC), Register Verification, Sequential Equivalence Checking (SEC), and Fault Injection / Functional Safety (ISO 26262).
Cross-Functional Leadership: Partner closely with Architecture and RTL Design teams to review specifications, identify corner-case bugs early, and improve design testability (DFT/DFV).
Mentorship & Process Improvement: Mentor junior verification engineers, establish best practices for formal specification, and integrate FV into CI/CD continuous integration pipelines.
Required Qualifications & Skills
Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication, Computer Engineering, or a related field.
Experience: 10+ years of dedicated hands-on experience in Formal Verification and RTL design/verification.
Formal Tools Mastery: Deep expertise in leading commercial formal tools (Cadence Jaspe Gold, Synopsys VC Formal, or Siemens Questa Formal).
Languages & Standards:
Fluent in SystemVerilog (SV), SystemVerilog Assertions (SVA), and Verilog/VHDL.
Strong scripting skills in Python, Tcl, or Perl for testbench automation and workflow optimization.
Design Knowledge: In-depth understanding of digital design fundamentals, pipeline architectures, multi-clock domain crossing (CDC/RDC), memory controllers, bus protocols (AXI, AHB, PCIe, CXI, CHI), and cache coherence protocols.
Advanced FV Techniques: Proven track record of resolving complex state-space convergence problems using abstraction models, assume-guarantee reasoning, and formal helper assertions.
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Key Responsibilities
Verification Architecture & Strategy: Define and execute end-to-end Formal Verification (FV) strategies for complex IPs, subsystems, and SoC-level control logic.
Formal Environment Setup: Build robust, reusable formal testbenches using industry-standard tools (e.g., Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal).
Property & Assertion Coding: Write high-quality, efficient SystemVerilog Assertions (SVA) and Property Specification Language (PSL) for safety properties, liveness properties, and invariants.
Abstraction & Problem Reduction: Develop advanced formal abstraction techniques (e.g., black-boxing, unrolling, symmetry reduction, case splitting, helper lemmas) to overcome state-space explosion and resolve formal convergence issues.
Coverage & Sign-off: Define formal coverage metrics (bounded proof coverage, core coverage), track verification completeness, and drive formal sign-off for critical blocks.
Formal Applications: Utilize specialized formal apps including Formal Connectivity, Equivalence Checking (LEC/CEC), Register Verification, Sequential Equivalence Checking (SEC), and Fault Injection / Functional Safety (ISO 26262).
Cross-Functional Leadership: Partner closely with Architecture and RTL Design teams to review specifications, identify corner-case bugs early, and improve design testability (DFT/DFV).
Mentorship & Process Improvement: Mentor junior verification engineers, establish best practices for formal specification, and integrate FV into CI/CD continuous integration pipelines.
Required Qualifications & Skills
Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication, Computer Engineering, or a related field.
Experience: 10+ years of dedicated hands-on experience in Formal Verification and RTL design/verification.
Formal Tools Mastery: Deep expertise in leading commercial formal tools (Cadence Jaspe Gold, Synopsys VC Formal, or Siemens Questa Formal).
Languages & Standards:
Fluent in SystemVerilog (SV), SystemVerilog Assertions (SVA), and Verilog/VHDL.
Strong scripting skills in Python, Tcl, or Perl for testbench automation and workflow optimization.
Design Knowledge: In-depth understanding of digital design fundamentals, pipeline architectures, multi-clock domain crossing (CDC/RDC), memory controllers, bus protocols (AXI, AHB, PCIe, CXI, CHI), and cache coherence protocols.
Advanced FV Techniques: Proven track record of resolving complex state-space convergence problems using abstraction models, assume-guarantee reasoning, and formal helper assertions.
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