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Formal Verification Engineer – AI/RTL Integration
Accepting applicationsCognichip · Redwood City, CA
Full-Time Mid_senior AIC++PythonRTLSystemVerilog
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Title
Formal Verification Engineer – AI/RTL Integration
About The Role
The landscape of hardware design is undergoing a paradigm shift. Large Language Models (LLMs) and advanced AI agents are increasingly capable of generating complex Register-Transfer Level (RTL) code. However, in silicon design, "almost correct" is not good enough. We are seeking a highly specialized Formal Verification Engineer to bridge the gap between artificial intelligence and hardware reliability. In this role, you will be responsible for developing the methodologies and automated flows required to mathematically prove the correctness of AI-generated RTL against high-level specifications. You will work closely with both our AI research team (who develop the generative models) and our hardware architecture team to ensure that AI-driven chip design is both rapid and flawlessly secure.
Key Responsibilities
Architect Verification Flows: Design and implement automated formal verification pipelines specifically tailored to evaluate, constrain, and verify Verilog/SystemVerilog code generated by AI models.
Property Specification: Translate natural language specifications, architectural documents, and high-level Python/C++ models into rigorous formal properties.
Proof & Debugging: Perform property checking, equivalence checking, and bounded model checking on AI-generated outputs.
AI Model Feedback Loop: Collaborate with AI researchers to design feedback mechanisms where formal verification failures are automatically translated into specialized prompts or training data to improve the AI's future RTL generation.
Mitigate Hallucinations: Develop strategies to detect and mathematically disprove logical hallucinations, security vulnerabilities, and edge-case failures introduced by generative AI in hardware designs.
Tool Integration: Write robust Python scripts and APIs to seamlessly interface LLM generation pipelines with Electronic Design Automation (EDA) verification environments.
Required Qualifications
Education: BS, MS, or Ph.D. in Computer Science, Applied Mathematics
Formal Verification Expertise: 3+ years of hands-on experience developing formal verification, property checking, and sequential equivalence checking tools.
Hardware Design: Understanding of digital logic design, computer architecture, and RTL coding (SystemVerilog/Verilog).
Programming Skills: Excellent scripting and programming abilities, particularly in Python, C++, or Rust, for building automation and interfacing with APIs.
AI Familiarity: A solid foundational understanding of modern machine learning, particularly Large Language Models (LLMs), prompt engineering, and how generative AI applies to coding tasks.
Preferred Qualifications
Theorem Proving: Experience with interactive theorem provers (e.g., Coq, Lean, ACL2) or advanced SMT solvers (e.g., Z3, CVC4).
EDA Tool Development: Previous experience building custom EDA tools or contributing to open-source hardware verification projects.
AI/ML Experience: Hands-on experience fine-tuning LLMs or working with AI agents for code generation.
Security: Background in hardware security and using formal methods to verify secure execution environments or cryptographic modules.
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Formal Verification Engineer – AI/RTL Integration
About The Role
The landscape of hardware design is undergoing a paradigm shift. Large Language Models (LLMs) and advanced AI agents are increasingly capable of generating complex Register-Transfer Level (RTL) code. However, in silicon design, "almost correct" is not good enough. We are seeking a highly specialized Formal Verification Engineer to bridge the gap between artificial intelligence and hardware reliability. In this role, you will be responsible for developing the methodologies and automated flows required to mathematically prove the correctness of AI-generated RTL against high-level specifications. You will work closely with both our AI research team (who develop the generative models) and our hardware architecture team to ensure that AI-driven chip design is both rapid and flawlessly secure.
Key Responsibilities
Architect Verification Flows: Design and implement automated formal verification pipelines specifically tailored to evaluate, constrain, and verify Verilog/SystemVerilog code generated by AI models.
Property Specification: Translate natural language specifications, architectural documents, and high-level Python/C++ models into rigorous formal properties.
Proof & Debugging: Perform property checking, equivalence checking, and bounded model checking on AI-generated outputs.
AI Model Feedback Loop: Collaborate with AI researchers to design feedback mechanisms where formal verification failures are automatically translated into specialized prompts or training data to improve the AI's future RTL generation.
Mitigate Hallucinations: Develop strategies to detect and mathematically disprove logical hallucinations, security vulnerabilities, and edge-case failures introduced by generative AI in hardware designs.
Tool Integration: Write robust Python scripts and APIs to seamlessly interface LLM generation pipelines with Electronic Design Automation (EDA) verification environments.
Required Qualifications
Education: BS, MS, or Ph.D. in Computer Science, Applied Mathematics
Formal Verification Expertise: 3+ years of hands-on experience developing formal verification, property checking, and sequential equivalence checking tools.
Hardware Design: Understanding of digital logic design, computer architecture, and RTL coding (SystemVerilog/Verilog).
Programming Skills: Excellent scripting and programming abilities, particularly in Python, C++, or Rust, for building automation and interfacing with APIs.
AI Familiarity: A solid foundational understanding of modern machine learning, particularly Large Language Models (LLMs), prompt engineering, and how generative AI applies to coding tasks.
Preferred Qualifications
Theorem Proving: Experience with interactive theorem provers (e.g., Coq, Lean, ACL2) or advanced SMT solvers (e.g., Z3, CVC4).
EDA Tool Development: Previous experience building custom EDA tools or contributing to open-source hardware verification projects.
AI/ML Experience: Hands-on experience fine-tuning LLMs or working with AI agents for code generation.
Security: Background in hardware security and using formal methods to verify secure execution environments or cryptographic modules.
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