Formal Verification

Skills And Qualifications • BSEE, Computer Engineering, or Computer Science bachelor’s degree and a minimum of 8+ years of experience o Masters or Ph.D. degree preferred • Strong experience or exposure to System Verilog (SV) and System Verilog Assertion (SVA) coding skills is required • Experience in developing formal verification setups is a must • Experience in developing constrained random testbenches is preferred • Experience with formal verification tools such as VC Formal, Jasper Gold, or Questa Formal • Experience working in a Linux environment • Excellent communication skills and be able to work with cross-functional teams to execute verification plan
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