Formal ASIC verification

Basic Qualifications
- Bachelor's degree in electrical engineering, computer engineering, or equivalent
- 8+ years of experience in ASIC/SoC design verification with a strong focus on formal verification
- Experience with JasperGold and/or Questa Formal
- Strong proficiency in SystemVerilog Assertions (SVA) and formal property specification
- Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
- Demonstrated ability to drive proof convergence on complex designs using abstraction, case-splitting, and assume-guarantee techniques
- Proficiency in SystemVerilog and UVM concepts
- Proficiency in leveraging AI/LLM tools to accelerate formal verification workflows including AI-assisted SVA generation, property debugging, proof exploration, and automated constraint refinement
Preferred Qualifications
- Master's or PhD in Electrical Engineering, Computer Engineering, or a related field with a focus on formal methods
- Experience verifying complex SoC designs including NoC/interconnect fabrics, memory subsystems, or communication protocol logic
- Familiarity with modem/PHY/DSP architectures or satellite communications systems
- Experience with scripting languages (Python, TCL, Perl) for flow automation and regression management
- Track record of finding critical silicon bugs using formal methods that escaped simulation
- Experience integrating formal verification into continuous integration (CI) workflows
- Familiarity with emulation-based verification and how formal methods complement emulation strategies
- Strong written and verbal communication skills with the ability to influence cross- functional teams
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