TJ
Field-Programmable Gate Arrays Engineer
Accepting applicationsThe Judge Group · Westminster, CO
Full-Time Mid_senior ARMC++FPGARTLSerDes
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Responsibilities:
Design, implement, and verify FPGA logic (RTL) for EOIR and other payloads on AMD Versal adaptive SoC and comparable architectures.
Develop embedded firmware across the payload stack — Versal processing system, supporting microcontrollers, boot and configuration, and device drivers.
Design and bring up detector-readout and sensor interfaces (focal-plane arrays / ROICs), including timing, control, and calibration paths.
Implement high-speed data interfaces and onboard signal- and image-processing chains (SerDes, CameraLink/CoaXPress/MIPI, SpaceWire/SpaceFibre; framing, corrections, compression).
Lead board bring-up and hardware/firmware integration, debugging at the boundary between hardware and firmware.
Integrate third-party and vendor IP cores, and coordinate with external developers and vendors to keep payload deliveries on schedule.
Maintain traceability from FPGA and firmware designs to top-level system requirements, and ensure designs meet applicable safety and performance standards.
Own verification: testbenches, simulation, timing closure, and hardware-in-the-loop validation.
Contribute to payload architecture, interface definition, and processor/component selection trades.
Qualifications:
BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, plus [5]+ years developing FPGA logic and firmware for payloads, instruments, or other high-reliability embedded systems.
Required Skills:
Strong RTL design in VHDL or Verilog, with real verification experience and timing closure on AMD/Xilinx toolchains (Vivado/Vitis) and a simulation tool such as ModelSim/QuestaSim.
Embedded firmware in C/C++ on SoC and microcontroller targets, bare-metal and/or RTOS.
Direct experience with AMD Versal or Zynq / Zynq UltraScale+-class adaptive SoCs, or a clear path from comparable SoC experience.
Experience with sensor/detector interfacing and high-speed data interfaces, and with on-FPGA DSP or image-processing chains.
Hardware and ARM-based SoC bring-up and lab debug: oscilloscope, logic analyzer, protocol analyzers, and schematic reading.
Must be able to obtain and hold a U.S. security clearance.
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Design, implement, and verify FPGA logic (RTL) for EOIR and other payloads on AMD Versal adaptive SoC and comparable architectures.
Develop embedded firmware across the payload stack — Versal processing system, supporting microcontrollers, boot and configuration, and device drivers.
Design and bring up detector-readout and sensor interfaces (focal-plane arrays / ROICs), including timing, control, and calibration paths.
Implement high-speed data interfaces and onboard signal- and image-processing chains (SerDes, CameraLink/CoaXPress/MIPI, SpaceWire/SpaceFibre; framing, corrections, compression).
Lead board bring-up and hardware/firmware integration, debugging at the boundary between hardware and firmware.
Integrate third-party and vendor IP cores, and coordinate with external developers and vendors to keep payload deliveries on schedule.
Maintain traceability from FPGA and firmware designs to top-level system requirements, and ensure designs meet applicable safety and performance standards.
Own verification: testbenches, simulation, timing closure, and hardware-in-the-loop validation.
Contribute to payload architecture, interface definition, and processor/component selection trades.
Qualifications:
BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, plus [5]+ years developing FPGA logic and firmware for payloads, instruments, or other high-reliability embedded systems.
Required Skills:
Strong RTL design in VHDL or Verilog, with real verification experience and timing closure on AMD/Xilinx toolchains (Vivado/Vitis) and a simulation tool such as ModelSim/QuestaSim.
Embedded firmware in C/C++ on SoC and microcontroller targets, bare-metal and/or RTOS.
Direct experience with AMD Versal or Zynq / Zynq UltraScale+-class adaptive SoCs, or a clear path from comparable SoC experience.
Experience with sensor/detector interfacing and high-speed data interfaces, and with on-FPGA DSP or image-processing chains.
Hardware and ARM-based SoC bring-up and lab debug: oscilloscope, logic analyzer, protocol analyzers, and schematic reading.
Must be able to obtain and hold a U.S. security clearance.
Show more Show less