Field-Programmable Gate Arrays Engineer

Senior FPGA Prototyping Engineer | 6+ Years | Bangalore

Location: Bangalore
Experience: 6+ Years
Role: Senior FPGA Prototyping Engineer
Job Summary
We are looking for an experienced FPGA Prototyping Engineer with 6+ years of hands-on experience in FPGA-based ASIC/SoC prototyping, RTL integration, FPGA implementation, debug and validation. The candidate should have strong knowledge of FPGA architecture, synthesis, timing closure, high-speed interfaces and hardware/software co-verification.

Key Responsibilities
Develop and maintain FPGA prototypes for complex ASIC/SoC designs.
Perform RTL integration, FPGA synthesis, implementation and bitstream generation.
Port large ASIC designs to FPGA prototyping platforms.
Analyze and resolve FPGA synthesis, implementation and timing issues.
Perform RTL modifications required for FPGA prototyping while maintaining ASIC functionality.
Develop FPGA constraints including XDC/SDC, clock constraints, I/O constraints and timing exceptions.
Perform timing analysis and timing closure on FPGA designs.
Debug RTL and FPGA hardware issues using simulation and on-board debug.
Use ILA/ChipScope/SignalTap for hardware debug and signal visibility.
Develop and execute FPGA bring-up and validation plans.
Support hardware/software co-verification and system-level validation.
Integrate processors, memories and peripheral IPs into FPGA prototypes.
Debug communication and high-speed interfaces.
Work with firmware/software teams to enable early software development on FPGA prototypes.
Automate FPGA build, regression and validation flows using scripting.
Collaborate with RTL, verification, ASIC, firmware, software and system teams.

FPGA Skills
Strong hands-on experience with one or more:
AMD/Xilinx FPGA
Vivado
Vitis
ILA
ChipScope
Zynq / Versal
Intel/Altera FPGA
Quartus
SignalTap
Platform Designer
FPGA synthesis and implementation.
FPGA floorplanning and resource optimization.
LUT, FF, BRAM, URAM and DSP utilization analysis.
Clocking resources, PLL/MMCM and reset architecture.
Timing closure and performance optimization.
Multi-clock domain design and CDC.
FPGA configuration and bitstream generation.

ASIC/SoC Prototyping
Experience converting ASIC RTL to FPGA-compatible RTL.
Handling ASIC-specific constructs that are not directly synthesizable on FPGA.
FPGA partitioning for large SoC designs.
Multi-FPGA partitioning and inter-FPGA communication.
Debugging FPGA prototype bring-up issues.
Experience with HAPS, Protium, Veloce, ZeBu or similar prototyping/emulation platforms is highly desirable.
Experience with FPGA-based pre-silicon validation.
Understanding of ASIC-to-FPGA implementation differences.

Interface Expertise
Experience with several of the following is preferred:
PCIe
Ethernet / 10G/25G/100G Ethernet
DDR3/DDR4/DDR5
USB
SATA
SPI
I2C
UART
AXI / AXI4 / AXI-Stream
MIPI
JESD
SerDes
AMBA protocols
High-speed transceivers

Verification & Debug
RTL simulation using VCS, Questa, Xcelium or equivalent.
FPGA hardware debug and waveform analysis.
ILA/SignalTap-based debug.
SystemVerilog/UVM knowledge is an advantage.
Functional validation and regression testing.
Debugging RTL, CDC, reset, clock and interface issues.
Familiarity with formal verification is a plus.
Scripting & Automation
Strong programming/scripting skills in:
Python
Tcl
Shell scripting
Perl is an advantage.

Experience automating:
FPGA builds
Synthesis/implementation flows
Regression
Bitstream generation
Log/report analysis
Hardware validation

Preferred Qualifications
B.E./B.Tech/M.E./M.Tech in ECE, EE, VLSI or equivalent.
6+ years of FPGA/ASIC prototyping experience.
Strong Verilog/SystemVerilog and RTL design knowledge.
Experience with complex SoC/IP-level FPGA prototypes.
Experience with FPGA timing closure and hardware debug.
Experience working across RTL, verification, firmware and software teams.
Experience with one or more Xilinx/AMD, Intel/Altera, Synopsys, Siemens or Cadence prototyping platforms.

Good-to-Have Skills
FPGA acceleration.
Hardware/software co-verification.
Emulation experience.
PCIe/DMA architecture.
DDR controller integration.
Multi-FPGA partitioning.
High-speed SerDes.
FPGA-based software validation.
Linux/embedded Linux.
U-Boot and device-tree knowledge.
ARM-based SoC platforms.
CI/CD-based FPGA build infrastructure.
Git/Jenkins automation.
Performance and resource optimization.
Silicon bring-up experience.

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