Ethernet Verification Engineer

Location: Hyderabad
Experience: 4–15 Years
Role Description
We are seeking a highly skilled Ethernet Verification Engineer to join our semiconductor engineering team. The ideal candidate will be responsible for validating complex Ethernet and Networking IPs within ASIC/SoC environments using industry-standard verification methodologies. This role involves developing robust verification environments, driving functional and performance verification, and ensuring high-quality silicon through comprehensive pre-silicon validation.
The successful candidate will work closely with Design, Architecture, and Validation teams to verify next-generation networking solutions used in data center, enterprise, and communication systems.
Key Responsibilities
Develop and execute comprehensive verification plans for Ethernet and Networking IPs.
Build, maintain, and enhance SystemVerilog/UVM-based verification environments.
Perform SoC-level RTL functional, performance, and power verification.
Develop testbenches, sequences, scoreboards, monitors, and verification components.
Create and maintain functional coverage models and assertion-based verification frameworks.
Execute constrained-random and coverage-driven verification methodologies.
Debug simulation failures, analyze waveforms, and identify root causes.
Validate Ethernet MAC, PHY, TSN, and high-speed networking subsystems.
Collaborate with design and architecture teams to resolve functional issues.
Participate in verification reviews, design reviews, and sign-off activities.
Drive coverage closure and ensure verification quality metrics are achieved.
Develop automation scripts for regression execution, reporting, and productivity improvements.
Support verification of power management, clocking, reset, and other SoC infrastructure blocks.
Required SkillsVerification Expertise
Strong experience in Pre-Silicon Verification of ASIC/SoC designs.
Expertise in SystemVerilog and UVM/OVM methodologies.
Experience with constrained-random verification and coverage-driven verification.
Strong understanding of functional coverage and assertion-based verification (SVA).
Experience with verification planning, execution, and sign-off.
Networking & Protocol Knowledge
Strong knowledge of Ethernet protocols (1G, 10G, 25G, 100G).
Experience with TSN (Time-Sensitive Networking) standards.
Understanding of MAC, PHY, SGMII, and XGMII interfaces.
Knowledge of networking architectures and Ethernet switch subsystems.
Technical Skills
Strong understanding of Digital Design, RTL, and Microarchitecture.
Experience with simulators such as Questasim, VCS, or Xcelium.
Proficiency in Python, Perl, or TCL scripting.
Knowledge of PCIe, DDR/Memory Controllers, Clocking, Reset, and Power Management subsystems.
Familiarity with Formal Verification, Lint, CDC, and RDC analysis is an added advantage.
Preferred Domain Experience
Candidates with experience in one or more of the following domains will be preferred:
Ethernet and Networking IP Verification
Data Center Networking Solutions
AI Accelerator Verification
Storage Controllers (NVMe, SAS)
TSN-Based Networking Systems
RAS (Reliability, Availability, Serviceability)
Power Management and SoC Infrastructure Verification
Qualifications
Bachelor's or Master's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
5–15 years of relevant experience in ASIC/SoC Verification.
Strong communication, analytical, and debugging skills.
Ability to work effectively in a fast-paced, collaborative engineering environment.

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