SI
Engineering, Architect
Accepting applicationsSynopsys Inc · Bengaluru, Karnataka, India
Full-Time Mid_senior AIASICRTLSynopsysai
Posted
5d ago
Category
Test
Experience
Mid_senior
Country
India
We Are
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent 15+ years in the trenches of physical design, taking complex soft IP from RTL to something that can actually tape out without blowing timing, power, or area budgets. Timing closure is not a mystery to you, it is a discipline you have mastered across multiple nodes and multiple product cycles. You know that the difference between a design that works on paper and one that a customer can actually implement is usually found in the floorplan decisions, the clock tree strategy, and the structural choices made six months before anyone ran Fusion Compiler.
Leadership comes naturally because you have been the person others turn to when a project is stuck at 95% timing closure or when a customer calls saying they cannot meet their PPA targets. You do not just manage engineers, you coach them through the hard problems. You know how to push back on a design team when the RTL needs rework, and you know how to do it in a way that builds collaboration instead of resentment.
At Synopsys, you will lead the team responsible for ensuring our HPC controller IP is not just functionally correct but physically feasible across real customer implementations. The IP you sign off on will ship to customers building the next generation of high-performance compute systems.
What You'll Be Doing
Lead a distributed team of physical design engineers executing multiple concurrent place-and-route projects across our HPC controller product portfolio
Own the physical feasibility sign-off process for all HPC controller soft IP releases, defining what "ready to ship" actually means in terms of timing, power, area, and customer implementability
Build and maintain physical user guides for each product vertical using a common template, translating complex floorplan and implementation strategies into actionable guidance customers can follow
Support customers directly during their implementation cycles, helping them navigate floorplan development, hierarchical flows, and node-specific challenges when integrating our IP
Develop the flows, scripts, and sign-off criteria that scale across the full configuration space of our HPC controllers, ensuring consistency and repeatability
Partner with RTL design teams to drive structural improvements, providing clear, assertive direction on what needs to change to enable physical success
Interface with methodology and EDA tool teams to drive improvements in Fusion Compiler flows, constraint generation, and automation that directly impact your team's productivity
The Impact You Will Have
Every soft IP release you sign off will be physically feasible with predictable runtimes, eliminating costly surprises for customers during their own implementation cycles
Design teams will deliver RTL that is ready for physical implementation, reducing iteration cycles and accelerating time to market
Customers will have a measurably better experience implementing our HPC IP, with clear guidance, high-quality constraints, and responsive support when they hit roadblocks
The collaboration between design and implementation teams will shift from reactive firefighting to proactive partnership, with shared accountability for physical outcomes
Your team will operate with clear sign-off criteria and repeatable flows, enabling them to scale across an expanding product portfolio without linear headcount growth
Leadership will have visibility into physical feasibility risks early enough to make informed tradeoffs on schedules, resources, and product commitments
You will build a culture where accountability and teamwork are not buzzwords but the actual way work gets done
What You'll Need
15+ years of hands-on experience in physical design and place-and-route, with a track record of taking complex designs through timing closure and tapeout
10+ years in leadership roles managing engineering teams, ideally in an ASIC or IP development environment
Deep expertise with Synopsys physical implementation tools, specifically Fusion Compiler, including hierarchical flows, clock tree synthesis, timing closure, and power optimization
Proven ability to manage multiple concurrent projects, balance competing priorities, and deliver results on schedule in a dynamic product development environment
Strong communication skills with the ability to influence cross-functional teams, present technical tradeoffs to leadership, and support customers through complex implementation challenges
Experience in HPC, networking, or high-speed controller IP development is a strong plus
Background in customer-facing technical support or field applications engineering is valuable but not required
Who You Are
You can walk into a review where timing is failing by 500ps and within 30 minutes identify whether the problem is in the RTL, the floorplan, the constraints, or the tool settings, and you can explain the path forward without jargon
When a design team pushes back on a structural change you are requesting, you do not escalate immediately, you bring data, show the impact, and build alignment through clarity and respect
You build teams that trust each other, where a junior engineer feels comfortable raising a risk early and a senior engineer does not hoard knowledge
Adaptability is second nature because you have lived through node transitions, standard updates, and tool version changes, and you know how to keep a team moving forward when the ground shifts
Results matter more to you than process, but you also know that repeatable process is what enables results at scale
You hold yourself and your team accountable, not through micromanagement but through clear expectations, regular check-ins, and a willingness to roll up your sleeves when the team needs it
The Team You'll Be Part Of
You will work with a high-impact High-Performance-Compute leadership team focused on delivery of complex IP to the marketplace. You will lead a horizontal team across the HPC product verticals, with resources reporting to you inserted into each of these verticals.
Rewards And Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Show more Show less
Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent 15+ years in the trenches of physical design, taking complex soft IP from RTL to something that can actually tape out without blowing timing, power, or area budgets. Timing closure is not a mystery to you, it is a discipline you have mastered across multiple nodes and multiple product cycles. You know that the difference between a design that works on paper and one that a customer can actually implement is usually found in the floorplan decisions, the clock tree strategy, and the structural choices made six months before anyone ran Fusion Compiler.
Leadership comes naturally because you have been the person others turn to when a project is stuck at 95% timing closure or when a customer calls saying they cannot meet their PPA targets. You do not just manage engineers, you coach them through the hard problems. You know how to push back on a design team when the RTL needs rework, and you know how to do it in a way that builds collaboration instead of resentment.
At Synopsys, you will lead the team responsible for ensuring our HPC controller IP is not just functionally correct but physically feasible across real customer implementations. The IP you sign off on will ship to customers building the next generation of high-performance compute systems.
What You'll Be Doing
Lead a distributed team of physical design engineers executing multiple concurrent place-and-route projects across our HPC controller product portfolio
Own the physical feasibility sign-off process for all HPC controller soft IP releases, defining what "ready to ship" actually means in terms of timing, power, area, and customer implementability
Build and maintain physical user guides for each product vertical using a common template, translating complex floorplan and implementation strategies into actionable guidance customers can follow
Support customers directly during their implementation cycles, helping them navigate floorplan development, hierarchical flows, and node-specific challenges when integrating our IP
Develop the flows, scripts, and sign-off criteria that scale across the full configuration space of our HPC controllers, ensuring consistency and repeatability
Partner with RTL design teams to drive structural improvements, providing clear, assertive direction on what needs to change to enable physical success
Interface with methodology and EDA tool teams to drive improvements in Fusion Compiler flows, constraint generation, and automation that directly impact your team's productivity
The Impact You Will Have
Every soft IP release you sign off will be physically feasible with predictable runtimes, eliminating costly surprises for customers during their own implementation cycles
Design teams will deliver RTL that is ready for physical implementation, reducing iteration cycles and accelerating time to market
Customers will have a measurably better experience implementing our HPC IP, with clear guidance, high-quality constraints, and responsive support when they hit roadblocks
The collaboration between design and implementation teams will shift from reactive firefighting to proactive partnership, with shared accountability for physical outcomes
Your team will operate with clear sign-off criteria and repeatable flows, enabling them to scale across an expanding product portfolio without linear headcount growth
Leadership will have visibility into physical feasibility risks early enough to make informed tradeoffs on schedules, resources, and product commitments
You will build a culture where accountability and teamwork are not buzzwords but the actual way work gets done
What You'll Need
15+ years of hands-on experience in physical design and place-and-route, with a track record of taking complex designs through timing closure and tapeout
10+ years in leadership roles managing engineering teams, ideally in an ASIC or IP development environment
Deep expertise with Synopsys physical implementation tools, specifically Fusion Compiler, including hierarchical flows, clock tree synthesis, timing closure, and power optimization
Proven ability to manage multiple concurrent projects, balance competing priorities, and deliver results on schedule in a dynamic product development environment
Strong communication skills with the ability to influence cross-functional teams, present technical tradeoffs to leadership, and support customers through complex implementation challenges
Experience in HPC, networking, or high-speed controller IP development is a strong plus
Background in customer-facing technical support or field applications engineering is valuable but not required
Who You Are
You can walk into a review where timing is failing by 500ps and within 30 minutes identify whether the problem is in the RTL, the floorplan, the constraints, or the tool settings, and you can explain the path forward without jargon
When a design team pushes back on a structural change you are requesting, you do not escalate immediately, you bring data, show the impact, and build alignment through clarity and respect
You build teams that trust each other, where a junior engineer feels comfortable raising a risk early and a senior engineer does not hoard knowledge
Adaptability is second nature because you have lived through node transitions, standard updates, and tool version changes, and you know how to keep a team moving forward when the ground shifts
Results matter more to you than process, but you also know that repeatable process is what enables results at scale
You hold yourself and your team accountable, not through micromanagement but through clear expectations, regular check-ins, and a willingness to roll up your sleeves when the team needs it
The Team You'll Be Part Of
You will work with a high-impact High-Performance-Compute leadership team focused on delivery of complex IP to the marketplace. You will lead a horizontal team across the HPC product verticals, with resources reporting to you inserted into each of these verticals.
Rewards And Benefits
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
Show more Show less