NS
DSP Engineer
Accepting applicationsNXP Semiconductors · Bengaluru, Karnataka, India
Full-Time Mid_senior C++DFTEthernetMATLABPython
Posted
30 May
Category
Design
Experience
Mid_senior
Country
India
We are looking for a DSP Engineer to join our Automotive Ethernet PHY team. You will work closely with the DSP Architect to implement DSP algorithms, contribute to PHY architecture realization, and support verification, validation, and backend teams throughout the product lifecycle.
Key Responsibilities
Implement and optimize DSP architecture for Automotive Ethernet PHY (100/1000BASE‑T1, Multi‑Gig).
Develop high‑quality RTL for DSP datapath blocks (filters, EQ, echo canceller, FFE/DFE, AGC, timing recovery).
Work with Verification/Validation for debugging, coverage closure, and model correlation.
Collaborate with DFT, System Architecture, IC Integration, and Backend teams for constraints and timing closure.
Develop MATLAB/Python models and support system‑level analysis.
Required Skills
Strong DSP and communication systems fundamentals.
Hands‑on experience with PHY‑layer DSP blocks.
RTL design expertise (Verilog/SystemVerilog).
MATLAB, Simulink, Python, C/C++ modeling experience.
Understanding of synthesis, STA, CDC, linting flows.
Good to Have
Experience with Automotive Ethernet PHY development.
Knowledge of DFT, post‑silicon bring‑up, and backend timing closure.
Exposure to UVM environments and formal verification.
If you're passionate about building next‑generation automotive PHY solutions, we’d love to talk!
More information about NXP in India...
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Key Responsibilities
Implement and optimize DSP architecture for Automotive Ethernet PHY (100/1000BASE‑T1, Multi‑Gig).
Develop high‑quality RTL for DSP datapath blocks (filters, EQ, echo canceller, FFE/DFE, AGC, timing recovery).
Work with Verification/Validation for debugging, coverage closure, and model correlation.
Collaborate with DFT, System Architecture, IC Integration, and Backend teams for constraints and timing closure.
Develop MATLAB/Python models and support system‑level analysis.
Required Skills
Strong DSP and communication systems fundamentals.
Hands‑on experience with PHY‑layer DSP blocks.
RTL design expertise (Verilog/SystemVerilog).
MATLAB, Simulink, Python, C/C++ modeling experience.
Understanding of synthesis, STA, CDC, linting flows.
Good to Have
Experience with Automotive Ethernet PHY development.
Knowledge of DFT, post‑silicon bring‑up, and backend timing closure.
Exposure to UVM environments and formal verification.
If you're passionate about building next‑generation automotive PHY solutions, we’d love to talk!
More information about NXP in India...
Show more Show less