LS
Director, DFx And Test Chip Engineering
Accepting applicationsLattice Semiconductor · Greater Chennai Area
Full-Time Principal AIASICDFTSoC
Posted
1d ago
Category
Manufacturing
Experience
Principal
Country
India
Company Description Lattice Semiconductor (NASDAQ: LSCC) is a leader in low power programmable solutions serving compute, communications, industrial, and embedded markets from the Edge to the Cloud. With the addition of AMI’s silicon-neutral platform firmware and infrastructure manageability solutions, Lattice now offers a comprehensive secure management and control platform for cloud and AI data center infrastructure. The company focuses on enabling customers to innovate quickly and efficiently, delivering technologies that help build a smart, secure, and connected world. Lattice is recognized for its strong customer relationships and commitment to world-class support. More information is available at www.latticesemi.com and through its presence on major social platforms.
Role Description The Director, DFx and Test Chip Engineering is a full-time, on-site leadership role based in the Greater Chennai Area. This role oversees design-for-test and design-for-manufacturability strategies for Lattice’s programmable solutions, ensuring robust test coverage and high-yield production. The director leads the planning, design, and validation of test chips, collaborating closely with architecture, design, product engineering, and manufacturing teams to optimize test methodologies and flows. Day-to-day responsibilities include managing an engineering team, defining DFx roadmaps, reviewing design and test plans, driving continuous improvement in test infrastructure, and resolving complex technical issues related to silicon bring-up and production test. The role also involves setting performance metrics, aligning projects with business objectives, and reporting progress to senior leadership.
Qualifications
Strong background in DFx (DFT/DFM/DFR) methodologies, with experience architecting test strategies for complex semiconductor devices.
Hands-on experience with test chip design, silicon validation, and production test flows for programmable logic or ASIC/SoC products.
Proficiency with EDA tools and industry-standard test environments, and familiarity with low-power design and verification practices.
Proven leadership skills in managing and mentoring engineering teams, including project planning, resource allocation, and performance management.
Ability to collaborate across functions with design, product engineering, manufacturing, and quality teams to drive end-to-end solutions.
Strong analytical and problem-solving skills, with the ability to diagnose complex silicon and test issues and implement data-driven improvements.
Excellent written and verbal communication skills, including the ability to present technical topics to both engineering and executive audiences.
Bachelor’s degree in Electrical Engineering, Electronics, or a related field; an advanced degree (Master’s or PhD) in a relevant discipline is preferred.
Experience in programmable logic, low-power devices, or cloud/AI data center infrastructure is highly beneficial.
Demonstrated track
Show more Show less
Role Description The Director, DFx and Test Chip Engineering is a full-time, on-site leadership role based in the Greater Chennai Area. This role oversees design-for-test and design-for-manufacturability strategies for Lattice’s programmable solutions, ensuring robust test coverage and high-yield production. The director leads the planning, design, and validation of test chips, collaborating closely with architecture, design, product engineering, and manufacturing teams to optimize test methodologies and flows. Day-to-day responsibilities include managing an engineering team, defining DFx roadmaps, reviewing design and test plans, driving continuous improvement in test infrastructure, and resolving complex technical issues related to silicon bring-up and production test. The role also involves setting performance metrics, aligning projects with business objectives, and reporting progress to senior leadership.
Qualifications
Strong background in DFx (DFT/DFM/DFR) methodologies, with experience architecting test strategies for complex semiconductor devices.
Hands-on experience with test chip design, silicon validation, and production test flows for programmable logic or ASIC/SoC products.
Proficiency with EDA tools and industry-standard test environments, and familiarity with low-power design and verification practices.
Proven leadership skills in managing and mentoring engineering teams, including project planning, resource allocation, and performance management.
Ability to collaborate across functions with design, product engineering, manufacturing, and quality teams to drive end-to-end solutions.
Strong analytical and problem-solving skills, with the ability to diagnose complex silicon and test issues and implement data-driven improvements.
Excellent written and verbal communication skills, including the ability to present technical topics to both engineering and executive audiences.
Bachelor’s degree in Electrical Engineering, Electronics, or a related field; an advanced degree (Master’s or PhD) in a relevant discipline is preferred.
Experience in programmable logic, low-power devices, or cloud/AI data center infrastructure is highly beneficial.
Demonstrated track
Show more Show less