Director, ASIC Design Verification

Director, SoC Design Verification

Location: Bengaluru (on-site, hours flexible)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD, Mediatek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

We are seeking a highly experienced and technically hands-on Director of SoC Design Verification to lead the verification strategy, methodology, infrastructure, and execution for next-generation SoCs targeting AI, networking, data center, communications, and high-performance computing applications.

The ideal candidate will possess deep expertise in architecting and verifying complex SoCs containing ARM and/or RISC-V processor subsystems, coherent interconnect fabrics, memory subsystems, high-speed I/O interfaces, and heterogeneous compute engines. This leader will be responsible for building and scaling world-class verification organizations, establishing SystemVerilog/UVM-based verification methodologies and flows from the ground up, driving verification closure, and ensuring first-pass silicon success.

The role requires strong technical leadership, hands-on verification expertise, and proven experience managing internal teams, external contractors, and third-party IP vendors across multiple sites and geographies.

Key Responsibilities

Verification Strategy and Technical Leadership

Define and drive the overall verification strategy, methodology, infrastructure, and execution plans across multiple SoC programs.
Establish verification quality metrics, coverage goals, signoff criteria, and tapeout readiness requirements.
Build, mentor, and scale high-performing verification teams across IP, subsystem, and SoC levels.
Lead verification planning from architecture definition through silicon bring-up and production release.
Drive continuous improvement of verification productivity, quality, automation, and reuse.
Partner closely with Architecture, Design, Physical Design, DFT, Firmware, Validation, Software, and Program Management teams.

SoC Verification Architecture

Lead verification of complex SoCs integrating:
ARM Cortex-A/R/M processor subsystems
RISC-V processor cores and subsystems
Coherent interconnect fabrics and Network-on-Chip (NoC) architectures
Cache coherency protocols including AMBA ACE, CHI, CCIX, CXL, and proprietary coherent fabrics
DDR, LPDDR, HBM, SRAM, and memory controller subsystems
Security, power management, clocking, reset, and system management infrastructure
AI, networking, storage, and accelerator subsystems
Define comprehensive verification plans, architecture-specific test strategies, and coverage models at IP, subsystem, and SoC levels.
Drive hardware/software co-verification and system-level validation methodologies.
Verification Methodology and Infrastructure Development

Architect and deploy scalable verification environments using SystemVerilog and UVM.
Establish verification methodologies and best practices from the ground up for new programs and organizations.
Define reusable testbench architectures supporting IP-to-SoC verification reuse.
Develop and standardize:
UVM frameworks
Verification components (UVCs)
Scoreboards
Checkers
Assertions
Functional coverage models
Reference models
Regression infrastructures
Drive adoption of constrained-random, coverage-driven, and assertion-based verification methodologies.
Build automated regression, CI/CD, debug, and reporting infrastructures.
Define verification signoff methodologies and coverage closure processes.
High-Speed I/O and SerDes Verification

Lead verification of advanced high-speed interface technologies, including:
PCI Express Gen5/Gen6
CXL
Ethernet (100G/200G/400G/800G)
UCIe
High-speed SerDes architectures
Chip-to-chip and die-to-die interfaces
Define protocol compliance, interoperability, stress, performance, and error-injection verification strategies.
Drive PHY, MAC, controller, subsystem, and SoC-level verification activities.
Collaborate with PHY, analog, packaging, and system teams to ensure robust end-to-end validation.
Advanced Verification Technologies

Drive deployment of formal verification, emulation, FPGA prototyping, simulation acceleration, and hybrid verification methodologies.
Establish scalable hardware/software co-verification environments.
Define performance, coherency, security, power-management, and system-level verification strategies.
Leverage data-driven methodologies and analytics for coverage closure and quality improvement.

Third-Party IP Integration and Qualification

Lead verification and integration of third-party IPs, including:
ARM processor cores
RISC-V cores
PCIe and CXL controllers
Ethernet MAC and PHY IPs
Security and cryptographic IP
Interconnect and NoC IP
Establish qualification, verification, and signoff methodologies for externally sourced IP.
Evaluate vendor verification collateral, test plans, assertions, compliance reports, and coverage metrics.
Define interoperability and integration testing strategies across internally developed and third-party IP.
Work closely with IP vendors to resolve technical, functional, performance, and quality issues.
Manage technical relationships with ecosystem partners, IP providers, and EDA vendors.
Organization and Contractor Management

Lead geographically distributed verification teams consisting of full-time employees, consultants, and offshore contractors.
Establish technical standards, coding guidelines, methodology requirements, and quality expectations across all teams.
Define contractor deliverables, milestones, verification metrics, and acceptance criteria.
Conduct regular design reviews, verification reviews, and quality audits.
Build organizational capabilities through mentoring, hiring, training, and succession planning.
Drive operational excellence and efficient execution across multiple programs and locations.

Required Qualifications

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
15+ years of semiconductor verification experience with a strong focus on complex SoC development.
5+ years of leadership experience managing verification organizations and technical teams.
Proven track record of delivering multiple successful SoCs from architecture through tapeout and silicon validation.
Deep expertise in SystemVerilog and UVM.
Extensive experience building verification methodologies, testbenches, and infrastructure from scratch.
Strong knowledge of ARM and/or RISC-V architectures and processor subsystem verification.
Extensive experience verifying cache-coherent and high-performance SoC architectures.
Deep understanding of AMBA protocols including AXI, AHB, APB, ACE, and CHI.
Strong expertise in high-speed I/O protocols including PCIe, CXL, Ethernet, UCIe, and SerDes-based interfaces.
Experience with constrained-random verification, coverage-driven verification, assertion-based verification, and formal verification methodologies.
Hands-on experience with simulation, emulation, FPGA prototyping, and hardware/software co-verification.
Demonstrated experience integrating and qualifying third-party IP from multiple vendors.
Proven ability to manage and scale internal teams, external contractors, and offshore verification organizations.

Preferred Qualifications

Experience with AI accelerator, networking, hyperscale infrastructure, storage, or data-center SoCs.
Experience with chiplet-based architectures and UCIe ecosystems.
Knowledge of advanced packaging technologies and heterogeneous integration.
Familiarity with firmware-driven verification and software-hardware co-design methodologies.
Experience with cloud-based regression and verification infrastructures.
Strong relationships within the semiconductor IP and EDA ecosystem.

Key Success Metrics

First-pass silicon success.
Verification coverage and closure quality.
Successful deployment of reusable verification methodologies across multiple programs.
Predictable execution against project schedules and tapeout milestones.
Effective integration and qualification of third-party IP.
High productivity and quality across internal and external verification teams.
Development and retention of top-tier verification talent.
Continuous improvement in automation, verification efficiency, and product quality.

Note To Recruiters

Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don’t send candidates to Ayar Labs, and do not contact our managers.
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