BS
Digital Implementation Engineer
Accepting applicationsBlack Sesame Technologies Inc · San Jose, CA
Full-Time Mid_senior AICadencePerlRTLSoC
Posted
2d ago
Category
Design
Experience
Mid_senior
Country
United States
About Black Sesame Technologies
Founded in 2016 and listed on the Hong Kong Stock Exchange (HKEX: 2533), Black Sesame Technologies is a leading provider of AI system-on-chip solutions. Our mass-produced AI chips are deployed across the automotive and robotics markets, delivering high-performance, automotive-grade computing solutions at scale
.As we develop our next generation of AI inference accelerators, we are rapidly expanding our R&D teams in Singapore and the United States. Join us and help build the foundational technologies powering the future of intelligent machines
.
Position Overvi
ewAs a Digital Implementation Engineer within our Core IP Design Team, you will contribute to the development and production of next-generation, high-performance, power-efficient AI cores and ADAS chip
s.This is a highly visible role responsible for synthesis, low-power implementation, timing closure, and close collaboration with physical design and SoC teams. You will play an important role in optimizing our designs for performance, power, and area while helping bring complex products to market efficientl
y.Responsibiliti
esLead synthesis and optimization efforts for IP cores, with a focus on performance, power, and area (PPA
).Collaborate with the physical design team on floorplanning, placement, routing, and timing closur
e.Work closely with the SoC team on clock, reset, timing, and power-related design requirement
s.Develop, maintain, and enhance synthesis, formal verification, and static timing analysis flow
s.Support the implementation and delivery of multiple complex IP block
s.Partner with SoC implementation engineers to integrate IP-level solutions into SoC-level design flow
s.Analyze implementation results and provide recommendations to improve RTL for higher frequency, lower power, and better physical design convergenc
e.Identify opportunities to improve design methodologies, automation, and overall engineering efficienc
y.Basic Qualificatio
nsBachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related fiel
d.At least 3 years of relevant industry experienc
e.Solid understanding of digital design and VLSI concept
s.Proficiency in Verilog and SystemVerilo
g.Hands-on experience with synthesis tools, particularly Synopsys Design Compile
r.Hands-on experience with static timing analysis using Synopsys PrimeTim
e.Experience with UPF-based low-power design and implementation flow
s.Experience with formal equivalence verification tools such as Cadence Conformal LEC and/or Synopsys Formalit
y.Proficiency in scripting languages such as Tcl, Perl, and Pytho
n.Strong analytical, problem-solving, and communication skill
s.Excellent attention to detail and a strong willingness to lear
n.Preferred Qualificatio
nsExperience implementing large-scale, high-frequency digital designs operating above 1 GH
z.Experience with physical synthesis and physically aware optimizatio
n.Strong understanding of physical design concepts, including floorplanning, placement, clock-tree synthesis, routing, and timing closur
e.Ability to review RTL and recommend improvements for timing, power, area, and physical implementatio
n.Experience developing AI accelerators, neural-network processors, or other high-performance compute chip
s.
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Founded in 2016 and listed on the Hong Kong Stock Exchange (HKEX: 2533), Black Sesame Technologies is a leading provider of AI system-on-chip solutions. Our mass-produced AI chips are deployed across the automotive and robotics markets, delivering high-performance, automotive-grade computing solutions at scale
.As we develop our next generation of AI inference accelerators, we are rapidly expanding our R&D teams in Singapore and the United States. Join us and help build the foundational technologies powering the future of intelligent machines
.
Position Overvi
ewAs a Digital Implementation Engineer within our Core IP Design Team, you will contribute to the development and production of next-generation, high-performance, power-efficient AI cores and ADAS chip
s.This is a highly visible role responsible for synthesis, low-power implementation, timing closure, and close collaboration with physical design and SoC teams. You will play an important role in optimizing our designs for performance, power, and area while helping bring complex products to market efficientl
y.Responsibiliti
esLead synthesis and optimization efforts for IP cores, with a focus on performance, power, and area (PPA
).Collaborate with the physical design team on floorplanning, placement, routing, and timing closur
e.Work closely with the SoC team on clock, reset, timing, and power-related design requirement
s.Develop, maintain, and enhance synthesis, formal verification, and static timing analysis flow
s.Support the implementation and delivery of multiple complex IP block
s.Partner with SoC implementation engineers to integrate IP-level solutions into SoC-level design flow
s.Analyze implementation results and provide recommendations to improve RTL for higher frequency, lower power, and better physical design convergenc
e.Identify opportunities to improve design methodologies, automation, and overall engineering efficienc
y.Basic Qualificatio
nsBachelor’s, Master’s, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related fiel
d.At least 3 years of relevant industry experienc
e.Solid understanding of digital design and VLSI concept
s.Proficiency in Verilog and SystemVerilo
g.Hands-on experience with synthesis tools, particularly Synopsys Design Compile
r.Hands-on experience with static timing analysis using Synopsys PrimeTim
e.Experience with UPF-based low-power design and implementation flow
s.Experience with formal equivalence verification tools such as Cadence Conformal LEC and/or Synopsys Formalit
y.Proficiency in scripting languages such as Tcl, Perl, and Pytho
n.Strong analytical, problem-solving, and communication skill
s.Excellent attention to detail and a strong willingness to lear
n.Preferred Qualificatio
nsExperience implementing large-scale, high-frequency digital designs operating above 1 GH
z.Experience with physical synthesis and physically aware optimizatio
n.Strong understanding of physical design concepts, including floorplanning, placement, clock-tree synthesis, routing, and timing closur
e.Ability to review RTL and recommend improvements for timing, power, area, and physical implementatio
n.Experience developing AI accelerators, neural-network processors, or other high-performance compute chip
s.
Show more Show less