MS
Digital IC Design Engineer
Accepting applicationsMarquee Semiconductor · Milpitas, CA
Full-Time Entry ASICCadenceCalibreFPGAGenus
Posted
6h ago
Category
Design
Experience
Entry
Country
United States
DUTIES:
Design and develop RTL modules for ASIC/SoC designs using Verilog/System Verilog.
Translate architectural specifications into synthesizable digital designs. Perform design trade-off analysis for performance, power, and area.
Create and maintain design documentation and specifications.
Debug design issues found during simulation, synthesis, and silicon validation.
Run lint, CDC, and other design quality checks. Collaborate with verification engineers to achieve functional coverage.
Integrate IP blocks and ensure proper interface functionality.
Work with physical design teams on timing constraints and closure.
Participate in design reviews and technical discussions.
Support backend implementation and silicon bring-up activities.
Support design and verification activities using standard engineering tools
REQUIREMENTS:
Bachelor’s degree or foreign academic equivalent in electrical engineering, Electronics Engineering, Electronics & Communications Engineering, Computer Engineering or related field.
Requires 12 months of experience in the job offered or as ASIC Design Engineer, RTL Design Engineer, FPGA Design Engineer, SoC Design Engineer, Hardware Design Engineer or Associate Engineer-Digital Design, Engineering or related field.
Requires experience in Design Quality: Synopsys Spyglass, Synthesis: Cadence Genus,o Design for Test: Modus, Place & Route: Innovus, Static Timing: Tempus, EMIR: Voltus, Circuits: Virtuoso, Physical Verification: Siemens Calibre.
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Design and develop RTL modules for ASIC/SoC designs using Verilog/System Verilog.
Translate architectural specifications into synthesizable digital designs. Perform design trade-off analysis for performance, power, and area.
Create and maintain design documentation and specifications.
Debug design issues found during simulation, synthesis, and silicon validation.
Run lint, CDC, and other design quality checks. Collaborate with verification engineers to achieve functional coverage.
Integrate IP blocks and ensure proper interface functionality.
Work with physical design teams on timing constraints and closure.
Participate in design reviews and technical discussions.
Support backend implementation and silicon bring-up activities.
Support design and verification activities using standard engineering tools
REQUIREMENTS:
Bachelor’s degree or foreign academic equivalent in electrical engineering, Electronics Engineering, Electronics & Communications Engineering, Computer Engineering or related field.
Requires 12 months of experience in the job offered or as ASIC Design Engineer, RTL Design Engineer, FPGA Design Engineer, SoC Design Engineer, Hardware Design Engineer or Associate Engineer-Digital Design, Engineering or related field.
Requires experience in Design Quality: Synopsys Spyglass, Synthesis: Cadence Genus,o Design for Test: Modus, Place & Route: Innovus, Static Timing: Tempus, EMIR: Voltus, Circuits: Virtuoso, Physical Verification: Siemens Calibre.
Show more Show less