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Digital Design RTL Engineer
Accepting applicationsBroadcom · Fort Collins, CO
Full-Time Mid_senior DDRRTLSerDesSoCSystemVerilog
Posted
6h ago
Category
Design
Experience
Mid_senior
Country
United States
Job Description:
Responsibilities include:
Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule
High proficiency in SystemVerilog
Proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of PPA optimization, clock domain crossing (CDC) analysis, and low-power design techniques.
Experience:
BSEE required, MSEE/PHD preferred
5+ years of industry experience with a focus on SoC integration, LPDDR5/6, DDR4/5 and/or high-speed SerDes, or HBM protocols is highly preferred.
Additional Job Description:
Compensation And Benefits
The annual base salary range for this position is $91,000 - $146,000.
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
R026042
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Responsibilities include:
Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule
High proficiency in SystemVerilog
Proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below) and possesses a deep understanding of PPA optimization, clock domain crossing (CDC) analysis, and low-power design techniques.
Experience:
BSEE required, MSEE/PHD preferred
5+ years of industry experience with a focus on SoC integration, LPDDR5/6, DDR4/5 and/or high-speed SerDes, or HBM protocols is highly preferred.
Additional Job Description:
Compensation And Benefits
The annual base salary range for this position is $91,000 - $146,000.
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
R026042
Show more Show less