A
Digital Design Engineer
Accepting applicationsActalent · Louisville, CO
Contract Mid_senior AIASICCadenceDFTPerl
Posted
1d ago
Category
Design
Experience
Mid_senior
Country
United States
Job Title: ASIC Digital Physical Design EngineerJob Description
Join a dynamic team where you will execute ASIC digital physical design implementation from RTL or gate-level netlist through GDSII. You will be working on cutting-edge projects, driving place-and-route execution using industry-standard EDA tools, and optimizing designs for timing, power, area, signal integrity, and routability.
Responsibilities
Execute ASIC digital physical design from RTL or gate-level netlist to GDSII, including floor-planning, placement, clock tree synthesis, routing, and design closure.
Drive place-and-route execution using industry-standard EDA tools, optimizing designs for timing, power, area, signal integrity, and routability.
Perform static timing analysis and timing verification across multiple modes and corners, resolving setup, hold, clocking, and constraint-related issues.
Support physical signoff activities, including DRC, LVS, formal equivalence checking, extraction, IR drop, electromigration, and signal integrity analysis.
Collaborate with RTL design, verification, DFT, analog, packaging, and product architecture teams to resolve implementation issues and ensure a timing-closed, manufacturable, tapeout-ready design.
Develop and maintain scripts, flows, documentation, and review materials to improve physical design methodology, automation, quality, and schedule predictability.
Essential Skills
BS in Electrical Engineering or equivalent experience.
5+ years of hands-on experience in ASIC physical design from RTL to verified GDS.
Hands-on experience with ASIC or SoC physical design implementation, including floorplanning, power planning, place-and-route, clock tree synthesis, routing, and design closure.
Experience with static timing analysis, timing constraints, multi-mode multi-corner timing verification, and timing closure at the block or SoC level.
Familiarity with physical signoff checks and related debug activities, including DRC, LVS, extraction, formal equivalence checking, IR drop, electromigration, and crosstalk analysis.
Proficiency with industry-standard physical design and timing tools from vendors such as Cadence, Synopsys, or Siemens EDA.
Strong scripting and automation skills using Tcl, Python, Perl, or shell scripting.
Additional Skills & Qualifications
10+ years of hands-on experience in ASIC physical design from RTL to verified GDS.
MS or PhD in Electrical Engineering or equivalent experience.
Principal-level experience leading physical design implementation for complex ASIC or SoC programs.
Proven ability to define and drive RTL-to-GDSII physical design strategy, resolve complex tradeoffs, and deliver tapeout-quality results on schedule.
Advanced expertise in static timing analysis, timing constraints, multi-mode multi-corner timing verification, clocking methodology, ECO implementation, and timing closure at the SoC, subsystem, and critical-block levels.
Deep experience driving physical signoff readiness and debug.
Expert proficiency with industry-standard physical design, timing, extraction, and signoff tools.
Demonstrated technical leadership managing internal execution and external ASIC design service providers.
Work Environment
This is a hybrid role, requiring at least 3 days in the office each week. We provide a collaborative environment where you can work on challenging projects that push the boundaries of technology. Join us in revolutionizing a better tomorrow.
Job Type & Location
This is a Contract to Hire position based out of Louisville, CO.
Pay And Benefits
The pay range for this position is $75.00 - $127.00/hr.
Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors.
Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following:
Medical, dental & vision
Critical Illness, Accident, and Hospital
401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available
Life Insurance (Voluntary Life & AD&D for the employee and dependents)
Short and long-term disability
Health Spending Account (HSA)
Transportation benefits
Employee Assistance Program
Time Off/Leave (PTO, Vacation or Sick Leave) Workplace Type This is a hybrid position in Louisville,CO. Application Deadline This position is anticipated to close on Sep 23, 2026.
About Actalent
Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.
The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.
If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email [email protected] for other accommodation options.
San Francisco Fair Chance Ordinance: Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.
Massachusetts Lie Detector: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.
Use of Artificial Intelligence (AI): We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.
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Join a dynamic team where you will execute ASIC digital physical design implementation from RTL or gate-level netlist through GDSII. You will be working on cutting-edge projects, driving place-and-route execution using industry-standard EDA tools, and optimizing designs for timing, power, area, signal integrity, and routability.
Responsibilities
Execute ASIC digital physical design from RTL or gate-level netlist to GDSII, including floor-planning, placement, clock tree synthesis, routing, and design closure.
Drive place-and-route execution using industry-standard EDA tools, optimizing designs for timing, power, area, signal integrity, and routability.
Perform static timing analysis and timing verification across multiple modes and corners, resolving setup, hold, clocking, and constraint-related issues.
Support physical signoff activities, including DRC, LVS, formal equivalence checking, extraction, IR drop, electromigration, and signal integrity analysis.
Collaborate with RTL design, verification, DFT, analog, packaging, and product architecture teams to resolve implementation issues and ensure a timing-closed, manufacturable, tapeout-ready design.
Develop and maintain scripts, flows, documentation, and review materials to improve physical design methodology, automation, quality, and schedule predictability.
Essential Skills
BS in Electrical Engineering or equivalent experience.
5+ years of hands-on experience in ASIC physical design from RTL to verified GDS.
Hands-on experience with ASIC or SoC physical design implementation, including floorplanning, power planning, place-and-route, clock tree synthesis, routing, and design closure.
Experience with static timing analysis, timing constraints, multi-mode multi-corner timing verification, and timing closure at the block or SoC level.
Familiarity with physical signoff checks and related debug activities, including DRC, LVS, extraction, formal equivalence checking, IR drop, electromigration, and crosstalk analysis.
Proficiency with industry-standard physical design and timing tools from vendors such as Cadence, Synopsys, or Siemens EDA.
Strong scripting and automation skills using Tcl, Python, Perl, or shell scripting.
Additional Skills & Qualifications
10+ years of hands-on experience in ASIC physical design from RTL to verified GDS.
MS or PhD in Electrical Engineering or equivalent experience.
Principal-level experience leading physical design implementation for complex ASIC or SoC programs.
Proven ability to define and drive RTL-to-GDSII physical design strategy, resolve complex tradeoffs, and deliver tapeout-quality results on schedule.
Advanced expertise in static timing analysis, timing constraints, multi-mode multi-corner timing verification, clocking methodology, ECO implementation, and timing closure at the SoC, subsystem, and critical-block levels.
Deep experience driving physical signoff readiness and debug.
Expert proficiency with industry-standard physical design, timing, extraction, and signoff tools.
Demonstrated technical leadership managing internal execution and external ASIC design service providers.
Work Environment
This is a hybrid role, requiring at least 3 days in the office each week. We provide a collaborative environment where you can work on challenging projects that push the boundaries of technology. Join us in revolutionizing a better tomorrow.
Job Type & Location
This is a Contract to Hire position based out of Louisville, CO.
Pay And Benefits
The pay range for this position is $75.00 - $127.00/hr.
Individual compensation offered for this position within this range will depend on many factors, including qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors.
Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following:
Medical, dental & vision
Critical Illness, Accident, and Hospital
401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available
Life Insurance (Voluntary Life & AD&D for the employee and dependents)
Short and long-term disability
Health Spending Account (HSA)
Transportation benefits
Employee Assistance Program
Time Off/Leave (PTO, Vacation or Sick Leave) Workplace Type This is a hybrid position in Louisville,CO. Application Deadline This position is anticipated to close on Sep 23, 2026.
About Actalent
Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.
The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.
If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email [email protected] for other accommodation options.
San Francisco Fair Chance Ordinance: Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.
Massachusetts Lie Detector: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.
Use of Artificial Intelligence (AI): We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.
Show more Show less