T
DFX Verification Engineer
Accepting applicationsTessolve · Greater Bengaluru Area
Full-Time Mid_senior SystemVerilogUVMScanMBISTLBIST
Posted
1d ago
Category
Test
Experience
Mid_senior
Country
India
🔍 Role: DFX Engineer
📍 Locations: Bengaluru | Chennai | Hyderabad | Noida
🧑 💻 Experience: 4–15 Years
⏳ Notice Period: Immediate to 30 Days
Key Responsibilities :
Develop and execute verification plans for DFx features including:
Scan (stuck-at, transition fault)
MBIST / LBIST
Boundary Scan (JTAG)
Memory repair and redundancy
Low-power test scenarios
Create and maintain testbenches using SystemVerilog/UVM for DFx validation
Verify:
Scan chain integrity and connectivity
Test mode functionality and coverage
ATPG pattern validation and debug
BIST controllers and memory test logic
#Technical Skills :
Strong knowledge of:
DFT concepts (Scan, ATPG, MBIST, JTAG)
Digital design fundamentals
Expertise in: SystemVerilog and UVM
Simulation tools (VCS, Xcelium, Questa)
Familiarity with: ATPG tools (TetraMAX, Modus, FastScan)
Debug tools (Verdi, DVE)
Understanding of:
Low-power design (UPF/CPF)
Clocking and reset strategies
📩 Interested? Apply now!
Send your resume to: sushma.siddaroda@tessolve.com
Show more Show less
📍 Locations: Bengaluru | Chennai | Hyderabad | Noida
🧑 💻 Experience: 4–15 Years
⏳ Notice Period: Immediate to 30 Days
Key Responsibilities :
Develop and execute verification plans for DFx features including:
Scan (stuck-at, transition fault)
MBIST / LBIST
Boundary Scan (JTAG)
Memory repair and redundancy
Low-power test scenarios
Create and maintain testbenches using SystemVerilog/UVM for DFx validation
Verify:
Scan chain integrity and connectivity
Test mode functionality and coverage
ATPG pattern validation and debug
BIST controllers and memory test logic
#Technical Skills :
Strong knowledge of:
DFT concepts (Scan, ATPG, MBIST, JTAG)
Digital design fundamentals
Expertise in: SystemVerilog and UVM
Simulation tools (VCS, Xcelium, Questa)
Familiarity with: ATPG tools (TetraMAX, Modus, FastScan)
Debug tools (Verdi, DVE)
Understanding of:
Low-power design (UPF/CPF)
Clocking and reset strategies
📩 Interested? Apply now!
Send your resume to: sushma.siddaroda@tessolve.com
Show more Show less