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DFT Verification Engineer
Accepting applicationsUST · Bengaluru, Karnataka, India
Full-Time Mid_senior ASICATEATPGBISTC++
Posted
1d ago
Category
Test
Experience
Mid_senior
Country
India
KEY RESPONSIBILITIES:
Develop and execute pre-silicon verification testplans for DFT features of the next generation Zen-architecture based CPU Cores
Develop directed and random verification tests to fully validate DFT functionality
Verify DFT design blocks and subsystems (such as JTAG/1500/1687, MBIST, Fuse, Clocks, Resets, etc.) using complex SV or C++ verification environments. Construct System Verilog and/or C/C++ models and test sequence libraries for simulation.
Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives.
Collaborate with architects and hardware engineers, and firmware engineers to understand the new features to be verified
Estimate the time required to write the new feature tests and any required changes to the test environment
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
Post silicon ATE and System level debug support of the test patterns delivered
PREFERRED EXPERIENCE:
Proficient in IP/SoC level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with Verilog, System Verilog, C, and C++
Strong background in the C++ language, preferably on Linux with exposure to Windows platform
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
Developing UVM based verification frameworks and testbenches, processes and flows
CPU architecture knowledge is desirable
Automating workflows in a distributed compute environment.
Scripting language experience: Perl, Ruby, Makefile, shell preferred.
DFT knowledge on Memory BIST, Logic BIST, Scan, ATPG is highly desirable
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Develop and execute pre-silicon verification testplans for DFT features of the next generation Zen-architecture based CPU Cores
Develop directed and random verification tests to fully validate DFT functionality
Verify DFT design blocks and subsystems (such as JTAG/1500/1687, MBIST, Fuse, Clocks, Resets, etc.) using complex SV or C++ verification environments. Construct System Verilog and/or C/C++ models and test sequence libraries for simulation.
Debug regression test failures to expose specification and implementation issues. Identify and address areas of concern to meet design quality objectives.
Collaborate with architects and hardware engineers, and firmware engineers to understand the new features to be verified
Estimate the time required to write the new feature tests and any required changes to the test environment
Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
Post silicon ATE and System level debug support of the test patterns delivered
PREFERRED EXPERIENCE:
Proficient in IP/SoC level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with Verilog, System Verilog, C, and C++
Strong background in the C++ language, preferably on Linux with exposure to Windows platform
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
Developing UVM based verification frameworks and testbenches, processes and flows
CPU architecture knowledge is desirable
Automating workflows in a distributed compute environment.
Scripting language experience: Perl, Ruby, Makefile, shell preferred.
DFT knowledge on Memory BIST, Logic BIST, Scan, ATPG is highly desirable
Show more Show less