DFT Scan & ATPG Engineer

Job Description
Design and implement DFT scan insertion for complex ASIC/SoC designs.
Develop, configure, and validate ATPG patterns for manufacturing test coverage.
Perform ATPG validation, coverage analysis, fault simulation, and pattern debugging.
Analyze and resolve scan-chain, DFT rule, timing, and ATPG-related issues.
Work closely with RTL, Physical Design, STA, and Silicon Validation teams to ensure DFT implementation meets design and test requirements.
Support DFT signoff and generate technical documentation for scan and ATPG flows.
Required Skills
8–12 years of hands-on DFT/Scan and ATPG experience.
Strong expertise in Scan Insertion and ATPG Validation.
Hands-on experience with Mentor Tessent (Siemens).
Strong experience with Synopsys DFT Compiler.
Experience with scan-chain debugging, ATPG coverage improvement, fault simulation, and DFT verification.
Good understanding of ASIC/SoC design flows, test methodologies, and DFT concepts.
Must-Have Skills
DFT Scan Insertion
ATPG Validation
Mentor Tessent (Siemens)
Synopsys DFT Compiler
Scan/ATPG Debugging & Coverage Analysis

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