ED
DFT Professionals_Eximietas Design
Accepting applicationsEximietas Design · Hyderabad, Telangana, India
Full-Time Mid_senior ASICATPGAnalogBoundary ScanCadence
Posted
6d ago
Category
Test
Experience
Mid_senior
Country
India
🚀 We’re Hiring – DFT Professional's | 5–20+ Years Experience
Greetings from Eximietas Design!
We are looking for experienced Design for Test (DFT) professionals to join our growing VLSI team. If you are passionate about advanced silicon testing and SoC design, this is a great opportunity to work on complex IP, Subsystem, and SoC level projects.
Locations:
India:
Bengaluru, Hyderabad & Visakhapatnam.
USA Eligibility:
USA: San Jose (Bay Area) / Austin
U.S. Permanent Residents (Green Card holders) only
🧑 💻 Experience: 5 – 20+ Years
🏢 Company: Eximietas Design
🔧 Role Overview
You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, subsystem, and SoC designs.
🎯 Core Responsibilities
Own the complete DFT implementation flow from RTL to pattern sign-off
Define and implement scan architectures including EDT and OCC
Perform block-level ATPG, DRC analysis, and coverage optimization
Execute pattern simulations (timing and non-timing)
Handle SoC-level integration and pattern retargeting
Integrate and debug MBIST, IJTAG, and Boundary Scan (JTAG)
Debug DFT simulations and netlist-related issues
Collaborate closely with design, verification, and physical design teams
Drive DFT sign-off activities and project deliverables
💻 Technical Requirements
Must-Have Skills
Strong expertise in netlist handling and ATPG simulations
Experience with block-level and SoC-level pattern retargeting
Understanding of ICL and PDL standards
Hands-on experience with DFT tool suites such as:
Siemens Tessent
Synopsys TestMAX / TetraMAX
Cadence Modus
Preferred Skills
Experience with Streaming Scan Network (SSN)
Knowledge of Analog & Mixed-Signal DFT methodologies
Exposure to SpyGlass for DFT linting
Experience in RTL-level DFT insertion
Strong scripting skills (TCL / Python / Perl)
🌟 Why Join Us?
✔ Work on cutting-edge semiconductor and SoC technologies
✔ Opportunity to collaborate with top industry experts
✔ Innovation-driven engineering culture
✔ Strong career growth opportunities
📩 Interested candidates can share their updated resume: maruthiprasad.e@eximietas.design
🤝 Referrals are highly appreciated!
Best Regards,
Maruthy Prasaad
Associate VLSI Manager – Talent Acquisition
📍 Visakhapatnam
📞 +91 8088969910
#DFT #VLSIJobs #ASIC #SemiconductorCareers #ATPG #ScanInsertion #Hiring #Eximietas
Show more Show less
Greetings from Eximietas Design!
We are looking for experienced Design for Test (DFT) professionals to join our growing VLSI team. If you are passionate about advanced silicon testing and SoC design, this is a great opportunity to work on complex IP, Subsystem, and SoC level projects.
Locations:
India:
Bengaluru, Hyderabad & Visakhapatnam.
USA Eligibility:
USA: San Jose (Bay Area) / Austin
U.S. Permanent Residents (Green Card holders) only
🧑 💻 Experience: 5 – 20+ Years
🏢 Company: Eximietas Design
🔧 Role Overview
You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, subsystem, and SoC designs.
🎯 Core Responsibilities
Own the complete DFT implementation flow from RTL to pattern sign-off
Define and implement scan architectures including EDT and OCC
Perform block-level ATPG, DRC analysis, and coverage optimization
Execute pattern simulations (timing and non-timing)
Handle SoC-level integration and pattern retargeting
Integrate and debug MBIST, IJTAG, and Boundary Scan (JTAG)
Debug DFT simulations and netlist-related issues
Collaborate closely with design, verification, and physical design teams
Drive DFT sign-off activities and project deliverables
💻 Technical Requirements
Must-Have Skills
Strong expertise in netlist handling and ATPG simulations
Experience with block-level and SoC-level pattern retargeting
Understanding of ICL and PDL standards
Hands-on experience with DFT tool suites such as:
Siemens Tessent
Synopsys TestMAX / TetraMAX
Cadence Modus
Preferred Skills
Experience with Streaming Scan Network (SSN)
Knowledge of Analog & Mixed-Signal DFT methodologies
Exposure to SpyGlass for DFT linting
Experience in RTL-level DFT insertion
Strong scripting skills (TCL / Python / Perl)
🌟 Why Join Us?
✔ Work on cutting-edge semiconductor and SoC technologies
✔ Opportunity to collaborate with top industry experts
✔ Innovation-driven engineering culture
✔ Strong career growth opportunities
📩 Interested candidates can share their updated resume: maruthiprasad.e@eximietas.design
🤝 Referrals are highly appreciated!
Best Regards,
Maruthy Prasaad
Associate VLSI Manager – Talent Acquisition
📍 Visakhapatnam
📞 +91 8088969910
#DFT #VLSIJobs #ASIC #SemiconductorCareers #ATPG #ScanInsertion #Hiring #Eximietas
Show more Show less