TC
DFT Manager
Accepting applicationsTalent Corner HR Services Pvt Ltd · Bangalore Urban, Karnataka, India
Full-Time Associate ATPGBISTCadenceDFTJTAG
Posted
1 Jun
Category
Test
Experience
Associate
Country
India
🚀 Hiring: Lead DFT Engineer / DFT Manager |
📍 Location: Bangalore, India
💼 Experience
10 – 18 Years
💰 Compensation
Best in the Industry
🌟 Join Us as a Lead DFT Engineer / DFT Manager!
Are you a highly experienced DFT professional passionate about driving end-to-end DFT strategy and execution for cutting-edge SoCs/IPs?
We are looking for a strong technical leader who can combine deep hands-on DFT expertise with leadership, ownership, and cross-functional collaboration to deliver high-quality silicon solutions.
If you thrive in complex semiconductor environments and enjoy mentoring teams while solving challenging DFT problems, we’d love to hear from you.
🔥 Key Responsibilities:
🧠 DFT Architecture & Strategy
Lead end-to-end DFT architecture, implementation, and signoff for complex SoC/IP programs
Define and drive DFT strategy covering:
Scan architectures
JTAG / iJTAG
BSCAN
ATPG
MBIST
Review and approve DFT plans, test architectures, and coverage targets.
⚙️ Execution & Signoff
Drive ATPG, MBIST, and DFT simulation flows with strong signoff ownership
Lead silicon bring-up, debug, and yield improvement activities from a DFT perspective
Ensure high test coverage, test quality, and robust validation methodologies.
👥 Leadership & Team Management
Lead, mentor, and guide a team of DFT engineers
Own technical reviews, task planning, and delivery milestones
Drive schedule management, risk mitigation, and execution excellence across projects.
🤝 Cross-Functional Collaboration
Work closely with Design, PD, Validation, Product, and Program teams
Conduct design and DFT reviews with internal and external stakeholders
Interface with customers and management on DFT status, risks, and execution plans.
✅ Required Technical Expertise
Strong hands-on experience in:
✔️ JTAG / iJTAG / BSCAN
✔️ Scan Architectures (Full Scan, Compression, Hierarchical DFT)
✔️ ATPG (Stuck-at, Transition, At-Speed Testing)
✔️ MBIST & Memory Test Strategies
✔️ DFT Simulation & Debug (RTL and Gate-Level)
✔️ SoC Test Architecture & Coverage Analysis.
Experience with industry-standard DFT tools:
Synopsys
Cadence
Siemens
Or equivalent tool suites
🎯 Leadership Expectations:
We are looking for professionals with proven experience as:
Team Lead
Technical Lead
DFT Manager
Hands-on experience in:
✔️ Team mentoring & technical leadership
✔️ DFT signoff ownership
✔️ Multi-project planning & execution
✔️ Stakeholder management & cross-functional coordination
✔️ Driving technical decisions and resolving complex DFT challenges.
🌟 Good to Have
➕ Low-Power DFT expertise
➕ IJTAG network implementation
➕ Advanced test compression techniques
➕ Experience handling large/complex SoCs
➕ Customer-facing or program leadership exposure
🎓 Education
B.Tech / M.Tech in Electronics, VLSI, or related field
Show more Show less
📍 Location: Bangalore, India
💼 Experience
10 – 18 Years
💰 Compensation
Best in the Industry
🌟 Join Us as a Lead DFT Engineer / DFT Manager!
Are you a highly experienced DFT professional passionate about driving end-to-end DFT strategy and execution for cutting-edge SoCs/IPs?
We are looking for a strong technical leader who can combine deep hands-on DFT expertise with leadership, ownership, and cross-functional collaboration to deliver high-quality silicon solutions.
If you thrive in complex semiconductor environments and enjoy mentoring teams while solving challenging DFT problems, we’d love to hear from you.
🔥 Key Responsibilities:
🧠 DFT Architecture & Strategy
Lead end-to-end DFT architecture, implementation, and signoff for complex SoC/IP programs
Define and drive DFT strategy covering:
Scan architectures
JTAG / iJTAG
BSCAN
ATPG
MBIST
Review and approve DFT plans, test architectures, and coverage targets.
⚙️ Execution & Signoff
Drive ATPG, MBIST, and DFT simulation flows with strong signoff ownership
Lead silicon bring-up, debug, and yield improvement activities from a DFT perspective
Ensure high test coverage, test quality, and robust validation methodologies.
👥 Leadership & Team Management
Lead, mentor, and guide a team of DFT engineers
Own technical reviews, task planning, and delivery milestones
Drive schedule management, risk mitigation, and execution excellence across projects.
🤝 Cross-Functional Collaboration
Work closely with Design, PD, Validation, Product, and Program teams
Conduct design and DFT reviews with internal and external stakeholders
Interface with customers and management on DFT status, risks, and execution plans.
✅ Required Technical Expertise
Strong hands-on experience in:
✔️ JTAG / iJTAG / BSCAN
✔️ Scan Architectures (Full Scan, Compression, Hierarchical DFT)
✔️ ATPG (Stuck-at, Transition, At-Speed Testing)
✔️ MBIST & Memory Test Strategies
✔️ DFT Simulation & Debug (RTL and Gate-Level)
✔️ SoC Test Architecture & Coverage Analysis.
Experience with industry-standard DFT tools:
Synopsys
Cadence
Siemens
Or equivalent tool suites
🎯 Leadership Expectations:
We are looking for professionals with proven experience as:
Team Lead
Technical Lead
DFT Manager
Hands-on experience in:
✔️ Team mentoring & technical leadership
✔️ DFT signoff ownership
✔️ Multi-project planning & execution
✔️ Stakeholder management & cross-functional coordination
✔️ Driving technical decisions and resolving complex DFT challenges.
🌟 Good to Have
➕ Low-Power DFT expertise
➕ IJTAG network implementation
➕ Advanced test compression techniques
➕ Experience handling large/complex SoCs
➕ Customer-facing or program leadership exposure
🎓 Education
B.Tech / M.Tech in Electronics, VLSI, or related field
Show more Show less